| #
3019c601 |
| 28-Nov-2024 |
xiaofeibao <[email protected]> |
timing(backend): pipe robCommits for better timing and area
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| #
63d67ef3 |
| 14-Sep-2024 |
Tang Haojin <[email protected]> |
build: enable always-basic-diff for make verilog (#3574)
This commit turns on basic difftest features again, no matter it's for
simulation or physical design. This commit aims at allowing designs f
build: enable always-basic-diff for make verilog (#3574)
This commit turns on basic difftest features again, no matter it's for
simulation or physical design. This commit aims at allowing designs for
physical design to be verified.
show more ...
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| #
bb2f3f51 |
| 12-Jul-2024 |
Tang Haojin <[email protected]> |
perf: use perfUtils in `Utility` (#3190)
Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies th
perf: use perfUtils in `Utility` (#3190)
Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies them and put them in Utility repository.
show more ...
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| #
ad5c9e6e |
| 04-Jul-2024 |
Junxiong Ji <[email protected]> |
RenameTable: fix width of rename table addr ports (#3128)
Different rename table has different numbers of entries, leading to
differences in the width of read/write ports. In the code we see the
w
RenameTable: fix width of rename table addr ports (#3128)
Different rename table has different numbers of entries, leading to
differences in the width of read/write ports. In the code we see the
widths of all read/write ports were set to 6, which works well but is
not parameterized. Now these widths are modified to be controlled by
parameters.
show more ...
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| #
d197680e |
| 31-May-2024 |
xiaofeibao <[email protected]> |
RenameTable: diff_rdata drop v0 for vec
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| #
2cf47c6e |
| 30-May-2024 |
xiaofeibao <[email protected]> |
Rename: VecLogicRegs change to 32+15
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| #
d1e473c9 |
| 30-May-2024 |
xiaofeibao <[email protected]> |
Rename: fix debug_v0_rat debug_vl_rat connection
|
| #
435f48a8 |
| 29-May-2024 |
xiaofeibao <[email protected]> |
Rename: add parameters V0LogicRegs VlLogicRegs
|
| #
368cbcec |
| 28-May-2024 |
xiaofeibao <[email protected]> |
Rename: v0 vl split
|
| #
4eebf274 |
| 25-Apr-2024 |
sinsanction <[email protected]> |
Rename: split fp and vec FreeList
|
| #
780712aa |
| 19-Mar-2024 |
xiaofeibao-xjtu <[email protected]> |
backend: new rob 8 banks read and 8 commit width
|
| #
5718c384 |
| 25-Mar-2024 |
Haojin Tang <[email protected]> |
Rename: remove old_pdest reading from RAT
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| #
5f8b6c9e |
| 07-Mar-2024 |
sinceforYy <[email protected]> |
Backend: add clock gating to valid singal
|
| #
63a2eab5 |
| 01-Mar-2024 |
zhanglyGit <[email protected]> |
RAT: optimize RenameTable read timing
|
| #
6b102a39 |
| 22-Nov-2023 |
Haojin Tang <[email protected]> |
Rab: shrink rab entry width
|
| #
cda1c534 |
| 24-Oct-2023 |
xiaofeibao-xjtu <[email protected]> |
Rob: optimize timing, remove vconfig debugIO
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| #
8d081717 |
| 24-Oct-2023 |
szw_kaixin <[email protected]> |
backend: control dontTouch opcode by debugEn
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| #
a3126b39 |
| 26-Oct-2023 |
xiaofeibao-xjtu <[email protected]> |
CtrlBlock optimize timing: read rat at rename stage, piped walkVtype to decode
|
| #
c4b56310 |
| 20-Oct-2023 |
Haojin Tang <[email protected]> |
snapshot: flush conditionally when redirect comes
|
| #
83ba63b3 |
| 11-Oct-2023 |
Xuan Hu <[email protected]> |
fix merge error
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| #
4b0d80d8 |
| 11-Oct-2023 |
Xuan Hu <[email protected]> |
Merge upstream/master into tmp-backend-merge-master
|
| #
b7d9e8d5 |
| 28-Sep-2023 |
xiaofeibao-xjtu <[email protected]> |
backend: parameterized generation debug IO and difftest IO
|
| #
8891a219 |
| 08-Oct-2023 |
Yinan Xu <[email protected]> |
Bump rocket-chip (#2353)
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| #
3cf50307 |
| 07-Sep-2023 |
Ziyue Zhang <[email protected]> |
vector: fix rename for vector instructions
* add old_pdest connection from vecRat to rename
|
| #
870f462d |
| 11-Aug-2023 |
Xuan Hu <[email protected]> |
fix errors in merge master into new-backend
|