1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility.HasCircularQueuePtrHelper 23import utility.ParallelPriorityMux 24import utils.XSError 25import xiangshan._ 26 27abstract class RegType 28case object Reg_I extends RegType 29case object Reg_F extends RegType 30case object Reg_V extends RegType 31 32class RatReadPort(implicit p: Parameters) extends XSBundle { 33 val hold = Input(Bool()) 34 val addr = Input(UInt(6.W)) 35 val data = Output(UInt(PhyRegIdxWidth.W)) 36} 37 38class RatWritePort(implicit p: Parameters) extends XSBundle { 39 val wen = Bool() 40 val addr = UInt(6.W) 41 val data = UInt(PhyRegIdxWidth.W) 42} 43 44class RenameTable(reg_t: RegType)(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper { 45 46 // params alias 47 private val numVecRegSrc = backendParams.numVecRegSrc 48 private val numVecRatPorts = numVecRegSrc + 1 // +1 dst 49 50 val readPortsNum = reg_t match { 51 case Reg_I => 3 52 case Reg_F => 4 53 case Reg_V => numVecRatPorts // +1 ldest 54 } 55 val io = IO(new Bundle { 56 val redirect = Input(Bool()) 57 val readPorts = Vec(readPortsNum * RenameWidth, new RatReadPort) 58 val specWritePorts = Vec(CommitWidth, Input(new RatWritePort)) 59 val archWritePorts = Vec(CommitWidth, Input(new RatWritePort)) 60 val old_pdest = Vec(CommitWidth, Output(UInt(PhyRegIdxWidth.W))) 61 val need_free = Vec(CommitWidth, Output(Bool())) 62 val snpt = Input(new SnapshotPort) 63 val diffWritePorts = if (backendParams.debugEn) Some(Vec(CommitWidth * MaxUopSize, Input(new RatWritePort))) else None 64 val debug_rdata = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 65 val debug_vconfig = if (backendParams.debugEn) reg_t match { // vconfig is implemented as int reg[32] 66 case Reg_V => Some(Output(UInt(PhyRegIdxWidth.W))) 67 case _ => None 68 } else None 69 val diff_rdata = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 70 val diff_vconfig = if (backendParams.debugEn) reg_t match { 71 case Reg_V => Some(Output(UInt(PhyRegIdxWidth.W))) 72 case _ => None 73 } else None 74 }) 75 76 // speculative rename table 77 // fp and vec share the same free list, so the first init value of vecRAT is 32 78 val rename_table_init = reg_t match { 79 case Reg_I => VecInit.fill (IntLogicRegs)(0.U(PhyRegIdxWidth.W)) 80 case Reg_F => VecInit.tabulate(FpLogicRegs)(_.U(PhyRegIdxWidth.W)) 81 case Reg_V => VecInit.tabulate(VecLogicRegs)(x => (x + FpLogicRegs).U(PhyRegIdxWidth.W)) 82 } 83 val spec_table = RegInit(rename_table_init) 84 val spec_table_next = WireInit(spec_table) 85 // arch state rename table 86 val arch_table = RegInit(rename_table_init) 87 val arch_table_next = WireDefault(arch_table) 88 // old_pdest 89 val old_pdest = RegInit(VecInit.fill(CommitWidth)(0.U(PhyRegIdxWidth.W))) 90 val need_free = RegInit(VecInit.fill(CommitWidth)(false.B)) 91 92 // For better timing, we optimize reading and writing to RenameTable as follows: 93 // (1) Writing at T0 will be actually processed at T1. 94 // (2) Reading is synchronous now. 95 // (3) RAddr at T0 will be used to access the table and get data at T0. 96 // (4) WData at T0 is bypassed to RData at T1. 97 val t1_redirect = RegNext(io.redirect, false.B) 98 val t1_raddr = io.readPorts.map(p => RegEnable(p.addr, !p.hold)) 99 val t1_rdata_use_t1_raddr = VecInit(t1_raddr.map(spec_table_next(_))) 100 val t1_wSpec = RegNext(Mux(io.redirect, 0.U.asTypeOf(io.specWritePorts), io.specWritePorts)) 101 102 val t1_snpt = RegNext(io.snpt, 0.U.asTypeOf(io.snpt)) 103 104 val snapshots = SnapshotGenerator(spec_table, t1_snpt.snptEnq, t1_snpt.snptDeq, t1_redirect, t1_snpt.flushVec) 105 106 // WRITE: when instruction commits or walking 107 val t1_wSpec_addr = t1_wSpec.map(w => Mux(w.wen, UIntToOH(w.addr), 0.U)) 108 for ((next, i) <- spec_table_next.zipWithIndex) { 109 val matchVec = t1_wSpec_addr.map(w => w(i)) 110 val wMatch = ParallelPriorityMux(matchVec.reverse, t1_wSpec.map(_.data).reverse) 111 // When there's a flush, we use arch_table to update spec_table. 112 next := Mux( 113 t1_redirect, 114 Mux(t1_snpt.useSnpt, snapshots(t1_snpt.snptSelect)(i), arch_table(i)), 115 Mux(VecInit(matchVec).asUInt.orR, wMatch, spec_table(i)) 116 ) 117 } 118 spec_table := spec_table_next 119 120 // READ: decode-rename stage 121 val a = io.specWritePorts.dropWhile(_ == io.specWritePorts(0)) 122 for ((r, i) <- io.readPorts.zipWithIndex) { 123 r.data := t1_rdata_use_t1_raddr(i) 124 } 125 126 for ((w, i) <- io.archWritePorts.zipWithIndex) { 127 when (w.wen) { 128 arch_table_next(w.addr) := w.data 129 } 130 val arch_mask = VecInit.fill(PhyRegIdxWidth)(w.wen).asUInt 131 old_pdest(i) := 132 MuxCase(arch_table(w.addr) & arch_mask, 133 io.archWritePorts.take(i).reverse.map(x => (x.wen && x.addr === w.addr, x.data & arch_mask))) 134 } 135 arch_table := arch_table_next 136 137 for (((old, free), i) <- (old_pdest zip need_free).zipWithIndex) { 138 val hasDuplicate = old_pdest.take(i).map(_ === old) 139 val blockedByDup = if (i == 0) false.B else VecInit(hasDuplicate).asUInt.orR 140 free := VecInit(arch_table.map(_ =/= old)).asUInt.andR && !blockedByDup 141 } 142 143 io.old_pdest := old_pdest 144 io.need_free := need_free 145 io.debug_rdata.foreach(_ := arch_table.take(32)) 146 io.debug_vconfig match { 147 case None => 148 case x => x.get := arch_table.last 149 } 150 if (env.EnableDifftest || env.AlwaysBasicDiff) { 151 val difftest_table = RegInit(rename_table_init) 152 val difftest_table_next = WireDefault(difftest_table) 153 154 for (w <- io.diffWritePorts.get) { 155 when(w.wen) { 156 difftest_table_next(w.addr) := w.data 157 } 158 } 159 difftest_table := difftest_table_next 160 161 io.diff_rdata.foreach(_ := difftest_table.take(32)) 162 io.diff_vconfig match { 163 case None => 164 case x => x.get := difftest_table(VCONFIG_IDX) 165 } 166 } 167 else { 168 io.diff_rdata.foreach(_ := 0.U.asTypeOf(io.debug_rdata.get)) 169 io.diff_vconfig match { 170 case None => 171 case x => x.get := 0.U 172 } 173 } 174} 175 176class RenameTableWrapper(implicit p: Parameters) extends XSModule { 177 178 // params alias 179 private val numVecRegSrc = backendParams.numVecRegSrc 180 private val numVecRatPorts = numVecRegSrc + 1 // +1 dst 181 182 val io = IO(new Bundle() { 183 val redirect = Input(Bool()) 184 val rabCommits = Input(new RabCommitIO) 185 val diffCommits = if (backendParams.debugEn) Some(Input(new DiffCommitIO)) else None 186 val intReadPorts = Vec(RenameWidth, Vec(3, new RatReadPort)) 187 val intRenamePorts = Vec(RenameWidth, Input(new RatWritePort)) 188 val fpReadPorts = Vec(RenameWidth, Vec(4, new RatReadPort)) 189 val fpRenamePorts = Vec(RenameWidth, Input(new RatWritePort)) 190 val vecReadPorts = Vec(RenameWidth, Vec(numVecRatPorts, new RatReadPort)) 191 val vecRenamePorts = Vec(RenameWidth, Input(new RatWritePort)) 192 193 val int_old_pdest = Vec(CommitWidth, Output(UInt(PhyRegIdxWidth.W))) 194 val fp_old_pdest = Vec(CommitWidth, Output(UInt(PhyRegIdxWidth.W))) 195 val vec_old_pdest = Vec(CommitWidth, Output(UInt(PhyRegIdxWidth.W))) 196 val int_need_free = Vec(CommitWidth, Output(Bool())) 197 val snpt = Input(new SnapshotPort) 198 199 // for debug printing 200 val debug_int_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 201 val debug_fp_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 202 val debug_vec_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 203 val debug_vconfig_rat = if (backendParams.debugEn) Some(Output(UInt(PhyRegIdxWidth.W))) else None 204 205 val diff_int_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 206 val diff_fp_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 207 val diff_vec_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 208 val diff_vconfig_rat = if (backendParams.debugEn) Some(Output(UInt(PhyRegIdxWidth.W))) else None 209 }) 210 211 val intRat = Module(new RenameTable(Reg_I)) 212 val fpRat = Module(new RenameTable(Reg_F)) 213 val vecRat = Module(new RenameTable(Reg_V)) 214 215 io.debug_int_rat .foreach(_ := intRat.io.debug_rdata.get) 216 io.diff_int_rat .foreach(_ := intRat.io.diff_rdata.get) 217 intRat.io.readPorts <> io.intReadPorts.flatten 218 intRat.io.redirect := io.redirect 219 intRat.io.snpt := io.snpt 220 io.int_old_pdest := intRat.io.old_pdest 221 io.int_need_free := intRat.io.need_free 222 val intDestValid = io.rabCommits.info.map(_.rfWen) 223 for ((arch, i) <- intRat.io.archWritePorts.zipWithIndex) { 224 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && intDestValid(i) 225 arch.addr := io.rabCommits.info(i).ldest 226 arch.data := io.rabCommits.info(i).pdest 227 XSError(arch.wen && arch.addr === 0.U && arch.data =/= 0.U, "pdest for $0 should be 0\n") 228 } 229 for ((spec, i) <- intRat.io.specWritePorts.zipWithIndex) { 230 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && intDestValid(i) 231 spec.addr := io.rabCommits.info(i).ldest 232 spec.data := io.rabCommits.info(i).pdest 233 XSError(spec.wen && spec.addr === 0.U && spec.data =/= 0.U, "pdest for $0 should be 0\n") 234 } 235 for ((spec, rename) <- intRat.io.specWritePorts.zip(io.intRenamePorts)) { 236 when (rename.wen) { 237 spec.wen := true.B 238 spec.addr := rename.addr 239 spec.data := rename.data 240 } 241 } 242 if (backendParams.debugEn) { 243 for ((diff, i) <- intRat.io.diffWritePorts.get.zipWithIndex) { 244 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).rfWen 245 diff.addr := io.diffCommits.get.info(i).ldest 246 diff.data := io.diffCommits.get.info(i).pdest 247 } 248 } 249 250 // debug read ports for difftest 251 io.debug_fp_rat.foreach(_ := fpRat.io.debug_rdata.get) 252 io.diff_fp_rat .foreach(_ := fpRat.io.diff_rdata.get) 253 fpRat.io.readPorts <> io.fpReadPorts.flatten 254 fpRat.io.redirect := io.redirect 255 fpRat.io.snpt := io.snpt 256 io.fp_old_pdest := fpRat.io.old_pdest 257 258 for ((arch, i) <- fpRat.io.archWritePorts.zipWithIndex) { 259 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && io.rabCommits.info(i).fpWen 260 arch.addr := io.rabCommits.info(i).ldest 261 arch.data := io.rabCommits.info(i).pdest 262 } 263 for ((spec, i) <- fpRat.io.specWritePorts.zipWithIndex) { 264 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && io.rabCommits.info(i).fpWen 265 spec.addr := io.rabCommits.info(i).ldest 266 spec.data := io.rabCommits.info(i).pdest 267 } 268 for ((spec, rename) <- fpRat.io.specWritePorts.zip(io.fpRenamePorts)) { 269 when (rename.wen) { 270 spec.wen := true.B 271 spec.addr := rename.addr 272 spec.data := rename.data 273 } 274 } 275 if (backendParams.debugEn) { 276 for ((diff, i) <- fpRat.io.diffWritePorts.get.zipWithIndex) { 277 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).fpWen 278 diff.addr := io.diffCommits.get.info(i).ldest 279 diff.data := io.diffCommits.get.info(i).pdest 280 } 281 } 282 // debug read ports for difftest 283 io.debug_vec_rat .foreach(_ := vecRat.io.debug_rdata.get) 284 io.debug_vconfig_rat.foreach(_ := vecRat.io.debug_vconfig.get) 285 io.diff_vec_rat .foreach(_ := vecRat.io.diff_rdata.get) 286 io.diff_vconfig_rat .foreach(_ := vecRat.io.diff_vconfig.get) 287 vecRat.io.readPorts <> io.vecReadPorts.flatten 288 vecRat.io.redirect := io.redirect 289 vecRat.io.snpt := io.snpt 290 io.vec_old_pdest := vecRat.io.old_pdest 291 292 //TODO: RM the donTouch 293 if(backendParams.debugEn) { 294 dontTouch(vecRat.io) 295 } 296 for ((arch, i) <- vecRat.io.archWritePorts.zipWithIndex) { 297 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && io.rabCommits.info(i).vecWen 298 arch.addr := io.rabCommits.info(i).ldest 299 arch.data := io.rabCommits.info(i).pdest 300 } 301 for ((spec, i) <- vecRat.io.specWritePorts.zipWithIndex) { 302 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && io.rabCommits.info(i).vecWen 303 spec.addr := io.rabCommits.info(i).ldest 304 spec.data := io.rabCommits.info(i).pdest 305 } 306 for ((spec, rename) <- vecRat.io.specWritePorts.zip(io.vecRenamePorts)) { 307 when (rename.wen) { 308 spec.wen := true.B 309 spec.addr := rename.addr 310 spec.data := rename.data 311 } 312 } 313 if (backendParams.debugEn) { 314 for ((diff, i) <- vecRat.io.diffWritePorts.get.zipWithIndex) { 315 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).vecWen 316 diff.addr := io.diffCommits.get.info(i).ldest 317 diff.data := io.diffCommits.get.info(i).pdest 318 } 319 } 320} 321