1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility.HasCircularQueuePtrHelper 23import utility.ParallelPriorityMux 24import utility.GatedValidRegNext 25import utils.XSError 26import xiangshan._ 27 28abstract class RegType 29case object Reg_I extends RegType 30case object Reg_F extends RegType 31case object Reg_V extends RegType 32case object Reg_V0 extends RegType 33case object Reg_Vl extends RegType 34 35class RatReadPort(implicit p: Parameters) extends XSBundle { 36 val hold = Input(Bool()) 37 val addr = Input(UInt(6.W)) 38 val data = Output(UInt(PhyRegIdxWidth.W)) 39} 40 41class RatWritePort(implicit p: Parameters) extends XSBundle { 42 val wen = Bool() 43 val addr = UInt(6.W) 44 val data = UInt(PhyRegIdxWidth.W) 45} 46 47class RenameTable(reg_t: RegType)(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper { 48 49 // params alias 50 private val numVecRegSrc = backendParams.numVecRegSrc 51 private val numVecRatPorts = numVecRegSrc 52 53 val readPortsNum = reg_t match { 54 case Reg_I => 2 55 case Reg_F => 3 56 case Reg_V => numVecRatPorts // +1 ldest 57 case Reg_V0 => 1 58 case Reg_Vl => 1 59 } 60 val rdataNums = reg_t match { 61 case Reg_I => 32 62 case Reg_F => 32 63 case Reg_V => 31 // no v0 64 case Reg_V0 => 1 // v0 65 case Reg_Vl => 1 // vl 66 } 67 val io = IO(new Bundle { 68 val redirect = Input(Bool()) 69 val readPorts = Vec(readPortsNum * RenameWidth, new RatReadPort) 70 val specWritePorts = Vec(RabCommitWidth, Input(new RatWritePort)) 71 val archWritePorts = Vec(RabCommitWidth, Input(new RatWritePort)) 72 val old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 73 val need_free = Vec(RabCommitWidth, Output(Bool())) 74 val snpt = Input(new SnapshotPort) 75 val diffWritePorts = if (backendParams.debugEn) Some(Vec(RabCommitWidth * MaxUopSize, Input(new RatWritePort))) else None 76 val debug_rdata = if (backendParams.debugEn) Some(Vec(rdataNums, Output(UInt(PhyRegIdxWidth.W)))) else None 77 val diff_rdata = if (backendParams.debugEn) Some(Vec(rdataNums, Output(UInt(PhyRegIdxWidth.W)))) else None 78 val debug_v0 = if (backendParams.debugEn) reg_t match { 79 case Reg_V0 => Some(Output(UInt(PhyRegIdxWidth.W))) 80 case _ => None 81 } else None 82 val diff_v0 = if (backendParams.debugEn) reg_t match { 83 case Reg_V0 => Some(Output(UInt(PhyRegIdxWidth.W))) 84 case _ => None 85 } else None 86 val debug_vl = if (backendParams.debugEn) reg_t match { 87 case Reg_Vl => Some(Output(UInt(PhyRegIdxWidth.W))) 88 case _ => None 89 } else None 90 val diff_vl = if (backendParams.debugEn) reg_t match { 91 case Reg_Vl => Some(Output(UInt(PhyRegIdxWidth.W))) 92 case _ => None 93 } else None 94 }) 95 96 // speculative rename table 97 val rename_table_init = reg_t match { 98 case Reg_I => VecInit.fill (IntLogicRegs)(0.U(PhyRegIdxWidth.W)) 99 case Reg_F => VecInit.tabulate(FpLogicRegs)(_.U(PhyRegIdxWidth.W)) 100 case Reg_V => VecInit.tabulate(VecLogicRegs)(_.U(PhyRegIdxWidth.W)) 101 case Reg_V0 => VecInit.tabulate(V0LogicRegs)(_.U(PhyRegIdxWidth.W)) 102 case Reg_Vl => VecInit.tabulate(VlLogicRegs)(_.U(PhyRegIdxWidth.W)) 103 } 104 val spec_table = RegInit(rename_table_init) 105 val spec_table_next = WireInit(spec_table) 106 // arch state rename table 107 val arch_table = RegInit(rename_table_init) 108 val arch_table_next = WireDefault(arch_table) 109 // old_pdest 110 val old_pdest = RegInit(VecInit.fill(RabCommitWidth)(0.U(PhyRegIdxWidth.W))) 111 val need_free = RegInit(VecInit.fill(RabCommitWidth)(false.B)) 112 113 // For better timing, we optimize reading and writing to RenameTable as follows: 114 // (1) Writing at T0 will be actually processed at T1. 115 // (2) Reading is synchronous now. 116 // (3) RAddr at T0 will be used to access the table and get data at T0. 117 // (4) WData at T0 is bypassed to RData at T1. 118 val t1_redirect = GatedValidRegNext(io.redirect, false.B) 119 val t1_raddr = io.readPorts.map(p => RegEnable(p.addr, !p.hold)) 120 val t1_rdata_use_t1_raddr = VecInit(t1_raddr.map(spec_table(_))) 121 val t1_wSpec = RegNext(Mux(io.redirect, 0.U.asTypeOf(io.specWritePorts), io.specWritePorts)) 122 123 val t1_snpt = RegNext(io.snpt, 0.U.asTypeOf(io.snpt)) 124 125 val snapshots = SnapshotGenerator(spec_table, t1_snpt.snptEnq, t1_snpt.snptDeq, t1_redirect, t1_snpt.flushVec) 126 127 // WRITE: when instruction commits or walking 128 val t1_wSpec_addr = t1_wSpec.map(w => Mux(w.wen, UIntToOH(w.addr), 0.U)) 129 for ((next, i) <- spec_table_next.zipWithIndex) { 130 val matchVec = t1_wSpec_addr.map(w => w(i)) 131 val wMatch = ParallelPriorityMux(matchVec.reverse, t1_wSpec.map(_.data).reverse) 132 // When there's a flush, we use arch_table to update spec_table. 133 next := Mux( 134 t1_redirect, 135 Mux(t1_snpt.useSnpt, snapshots(t1_snpt.snptSelect)(i), arch_table(i)), 136 Mux(VecInit(matchVec).asUInt.orR, wMatch, spec_table(i)) 137 ) 138 } 139 spec_table := spec_table_next 140 141 // READ: decode-rename stage 142 for ((r, i) <- io.readPorts.zipWithIndex) { 143 val t0_bypass = io.specWritePorts.map(w => w.wen && Mux(r.hold, w.addr === t1_raddr(i), w.addr === r.addr)) 144 val t1_bypass = RegNext(Mux(io.redirect, 0.U.asTypeOf(VecInit(t0_bypass)), VecInit(t0_bypass))) 145 val bypass_data = ParallelPriorityMux(t1_bypass.reverse, t1_wSpec.map(_.data).reverse) 146 r.data := Mux(t1_bypass.asUInt.orR, bypass_data, t1_rdata_use_t1_raddr(i)) 147 } 148 149 for ((w, i) <- io.archWritePorts.zipWithIndex) { 150 when (w.wen) { 151 arch_table_next(w.addr) := w.data 152 } 153 val arch_mask = VecInit.fill(PhyRegIdxWidth)(w.wen).asUInt 154 old_pdest(i) := 155 MuxCase(arch_table(w.addr) & arch_mask, 156 io.archWritePorts.take(i).reverse.map(x => (x.wen && x.addr === w.addr, x.data & arch_mask))) 157 } 158 arch_table := arch_table_next 159 160 for (((old, free), i) <- (old_pdest zip need_free).zipWithIndex) { 161 val hasDuplicate = old_pdest.take(i).map(_ === old) 162 val blockedByDup = if (i == 0) false.B else VecInit(hasDuplicate).asUInt.orR 163 free := VecInit(arch_table.map(_ =/= old)).asUInt.andR && !blockedByDup 164 } 165 166 io.old_pdest := old_pdest 167 io.need_free := need_free 168 io.debug_rdata.foreach(_ := arch_table.take(rdataNums)) 169 io.debug_v0.foreach(_ := arch_table(0)) 170 io.debug_vl.foreach(_ := arch_table(0)) 171 if (env.EnableDifftest || env.AlwaysBasicDiff) { 172 val difftest_table = RegInit(rename_table_init) 173 val difftest_table_next = WireDefault(difftest_table) 174 175 for (w <- io.diffWritePorts.get) { 176 when(w.wen) { 177 difftest_table_next(w.addr) := w.data 178 } 179 } 180 difftest_table := difftest_table_next 181 182 io.diff_rdata.foreach(_ := difftest_table.take(rdataNums)) 183 io.diff_v0.foreach(_ := difftest_table(0)) 184 io.diff_vl.foreach(_ := difftest_table(0)) 185 } 186 else { 187 io.diff_rdata.foreach(_ := 0.U.asTypeOf(io.debug_rdata.get)) 188 io.diff_v0.foreach(_ := 0.U) 189 io.diff_vl.foreach(_ := 0.U) 190 } 191} 192 193class RenameTableWrapper(implicit p: Parameters) extends XSModule { 194 195 // params alias 196 private val numVecRegSrc = backendParams.numVecRegSrc 197 private val numVecRatPorts = numVecRegSrc 198 199 val io = IO(new Bundle() { 200 val redirect = Input(Bool()) 201 val rabCommits = Input(new RabCommitIO) 202 val diffCommits = if (backendParams.debugEn) Some(Input(new DiffCommitIO)) else None 203 val intReadPorts = Vec(RenameWidth, Vec(2, new RatReadPort)) 204 val intRenamePorts = Vec(RenameWidth, Input(new RatWritePort)) 205 val fpReadPorts = Vec(RenameWidth, Vec(3, new RatReadPort)) 206 val fpRenamePorts = Vec(RenameWidth, Input(new RatWritePort)) 207 val vecReadPorts = Vec(RenameWidth, Vec(numVecRatPorts, new RatReadPort)) 208 val vecRenamePorts = Vec(RenameWidth, Input(new RatWritePort)) 209 val v0ReadPorts = Vec(RenameWidth, new RatReadPort) 210 val v0RenamePorts = Vec(RenameWidth, Input(new RatWritePort)) 211 val vlReadPorts = Vec(RenameWidth, new RatReadPort) 212 val vlRenamePorts = Vec(RenameWidth, Input(new RatWritePort)) 213 214 val int_old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 215 val fp_old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 216 val vec_old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 217 val v0_old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 218 val vl_old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 219 val int_need_free = Vec(RabCommitWidth, Output(Bool())) 220 val snpt = Input(new SnapshotPort) 221 222 // for debug printing 223 val debug_int_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 224 val debug_fp_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 225 val debug_vec_rat = if (backendParams.debugEn) Some(Vec(31, Output(UInt(PhyRegIdxWidth.W)))) else None 226 val debug_v0_rat = if (backendParams.debugEn) Some(Output(UInt(PhyRegIdxWidth.W))) else None 227 val debug_vl_rat = if (backendParams.debugEn) Some(Output(UInt(PhyRegIdxWidth.W))) else None 228 229 val diff_int_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 230 val diff_fp_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 231 val diff_vec_rat = if (backendParams.debugEn) Some(Vec(31, Output(UInt(PhyRegIdxWidth.W)))) else None 232 val diff_v0_rat = if (backendParams.debugEn) Some(Output(UInt(PhyRegIdxWidth.W))) else None 233 val diff_vl_rat = if (backendParams.debugEn) Some(Output(UInt(PhyRegIdxWidth.W))) else None 234 }) 235 236 val intRat = Module(new RenameTable(Reg_I)) 237 val fpRat = Module(new RenameTable(Reg_F)) 238 val vecRat = Module(new RenameTable(Reg_V)) 239 val v0Rat = Module(new RenameTable(Reg_V0)) 240 val vlRat = Module(new RenameTable(Reg_Vl)) 241 242 io.debug_int_rat .foreach(_ := intRat.io.debug_rdata.get) 243 io.diff_int_rat .foreach(_ := intRat.io.diff_rdata.get) 244 intRat.io.readPorts <> io.intReadPorts.flatten 245 intRat.io.redirect := io.redirect 246 intRat.io.snpt := io.snpt 247 io.int_old_pdest := intRat.io.old_pdest 248 io.int_need_free := intRat.io.need_free 249 val intDestValid = io.rabCommits.info.map(_.rfWen) 250 for ((arch, i) <- intRat.io.archWritePorts.zipWithIndex) { 251 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && intDestValid(i) 252 arch.addr := io.rabCommits.info(i).ldest 253 arch.data := io.rabCommits.info(i).pdest 254 XSError(arch.wen && arch.addr === 0.U && arch.data =/= 0.U, "pdest for $0 should be 0\n") 255 } 256 for ((spec, i) <- intRat.io.specWritePorts.zipWithIndex) { 257 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && intDestValid(i) 258 spec.addr := io.rabCommits.info(i).ldest 259 spec.data := io.rabCommits.info(i).pdest 260 XSError(spec.wen && spec.addr === 0.U && spec.data =/= 0.U, "pdest for $0 should be 0\n") 261 } 262 for ((spec, rename) <- intRat.io.specWritePorts.zip(io.intRenamePorts)) { 263 when (rename.wen) { 264 spec.wen := true.B 265 spec.addr := rename.addr 266 spec.data := rename.data 267 } 268 } 269 if (backendParams.debugEn) { 270 for ((diff, i) <- intRat.io.diffWritePorts.get.zipWithIndex) { 271 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).rfWen 272 diff.addr := io.diffCommits.get.info(i).ldest 273 diff.data := io.diffCommits.get.info(i).pdest 274 } 275 } 276 277 // debug read ports for difftest 278 io.debug_fp_rat.foreach(_ := fpRat.io.debug_rdata.get) 279 io.diff_fp_rat .foreach(_ := fpRat.io.diff_rdata.get) 280 fpRat.io.readPorts <> io.fpReadPorts.flatten 281 fpRat.io.redirect := io.redirect 282 fpRat.io.snpt := io.snpt 283 io.fp_old_pdest := fpRat.io.old_pdest 284 285 for ((arch, i) <- fpRat.io.archWritePorts.zipWithIndex) { 286 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && io.rabCommits.info(i).fpWen 287 arch.addr := io.rabCommits.info(i).ldest 288 arch.data := io.rabCommits.info(i).pdest 289 } 290 for ((spec, i) <- fpRat.io.specWritePorts.zipWithIndex) { 291 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && io.rabCommits.info(i).fpWen 292 spec.addr := io.rabCommits.info(i).ldest 293 spec.data := io.rabCommits.info(i).pdest 294 } 295 for ((spec, rename) <- fpRat.io.specWritePorts.zip(io.fpRenamePorts)) { 296 when (rename.wen) { 297 spec.wen := true.B 298 spec.addr := rename.addr 299 spec.data := rename.data 300 } 301 } 302 if (backendParams.debugEn) { 303 for ((diff, i) <- fpRat.io.diffWritePorts.get.zipWithIndex) { 304 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).fpWen 305 diff.addr := io.diffCommits.get.info(i).ldest 306 diff.data := io.diffCommits.get.info(i).pdest 307 } 308 } 309 310 // debug read ports for difftest 311 io.debug_vec_rat .foreach(_ := vecRat.io.debug_rdata.get) 312 io.diff_vec_rat .foreach(_ := vecRat.io.diff_rdata.get) 313 vecRat.io.readPorts <> io.vecReadPorts.flatten 314 vecRat.io.redirect := io.redirect 315 vecRat.io.snpt := io.snpt 316 io.vec_old_pdest := vecRat.io.old_pdest 317 318 //TODO: RM the donTouch 319 if(backendParams.debugEn) { 320 dontTouch(vecRat.io) 321 } 322 for ((arch, i) <- vecRat.io.archWritePorts.zipWithIndex) { 323 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && io.rabCommits.info(i).vecWen 324 arch.addr := io.rabCommits.info(i).ldest 325 arch.data := io.rabCommits.info(i).pdest 326 } 327 for ((spec, i) <- vecRat.io.specWritePorts.zipWithIndex) { 328 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && io.rabCommits.info(i).vecWen 329 spec.addr := io.rabCommits.info(i).ldest 330 spec.data := io.rabCommits.info(i).pdest 331 } 332 for ((spec, rename) <- vecRat.io.specWritePorts.zip(io.vecRenamePorts)) { 333 when (rename.wen) { 334 spec.wen := true.B 335 spec.addr := rename.addr 336 spec.data := rename.data 337 } 338 } 339 if (backendParams.debugEn) { 340 for ((diff, i) <- vecRat.io.diffWritePorts.get.zipWithIndex) { 341 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).vecWen 342 diff.addr := io.diffCommits.get.info(i).ldest 343 diff.data := io.diffCommits.get.info(i).pdest 344 } 345 } 346 347 // debug read ports for difftest 348 io.debug_v0_rat.foreach(_ := v0Rat.io.debug_rdata.get) 349 io.diff_v0_rat.foreach(_ := v0Rat.io.diff_rdata.get) 350 v0Rat.io.readPorts <> io.v0ReadPorts 351 v0Rat.io.redirect := io.redirect 352 v0Rat.io.snpt := io.snpt 353 io.v0_old_pdest := v0Rat.io.old_pdest 354 355 if (backendParams.debugEn) { 356 dontTouch(v0Rat.io) 357 } 358 for ((arch, i) <- v0Rat.io.archWritePorts.zipWithIndex) { 359 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && io.rabCommits.info(i).v0Wen 360 arch.addr := io.rabCommits.info(i).ldest 361 arch.data := io.rabCommits.info(i).pdest 362 } 363 for ((spec, i) <- v0Rat.io.specWritePorts.zipWithIndex) { 364 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && io.rabCommits.info(i).v0Wen 365 spec.addr := io.rabCommits.info(i).ldest 366 spec.data := io.rabCommits.info(i).pdest 367 } 368 for ((spec, rename) <- v0Rat.io.specWritePorts.zip(io.v0RenamePorts)) { 369 when(rename.wen) { 370 spec.wen := true.B 371 spec.addr := rename.addr 372 spec.data := rename.data 373 } 374 } 375 if (backendParams.debugEn) { 376 for ((diff, i) <- v0Rat.io.diffWritePorts.get.zipWithIndex) { 377 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).v0Wen 378 diff.addr := io.diffCommits.get.info(i).ldest 379 diff.data := io.diffCommits.get.info(i).pdest 380 } 381 } 382 383 // debug read ports for difftest 384 io.debug_vl_rat.foreach(_ := vlRat.io.debug_rdata.get) 385 io.diff_vl_rat.foreach(_ := vlRat.io.diff_rdata.get) 386 vlRat.io.readPorts <> io.vlReadPorts 387 vlRat.io.redirect := io.redirect 388 vlRat.io.snpt := io.snpt 389 io.vl_old_pdest := vlRat.io.old_pdest 390 391 if (backendParams.debugEn) { 392 dontTouch(vlRat.io) 393 } 394 for ((arch, i) <- vlRat.io.archWritePorts.zipWithIndex) { 395 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && io.rabCommits.info(i).vlWen 396 arch.addr := io.rabCommits.info(i).ldest 397 arch.data := io.rabCommits.info(i).pdest 398 } 399 for ((spec, i) <- vlRat.io.specWritePorts.zipWithIndex) { 400 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && io.rabCommits.info(i).vlWen 401 spec.addr := io.rabCommits.info(i).ldest 402 spec.data := io.rabCommits.info(i).pdest 403 } 404 for ((spec, rename) <- vlRat.io.specWritePorts.zip(io.vlRenamePorts)) { 405 when(rename.wen) { 406 spec.wen := true.B 407 spec.addr := rename.addr 408 spec.data := rename.data 409 } 410 } 411 if (backendParams.debugEn) { 412 for ((diff, i) <- vlRat.io.diffWritePorts.get.zipWithIndex) { 413 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).vlWen 414 diff.addr := io.diffCommits.get.info(i).ldest 415 diff.data := io.diffCommits.get.info(i).pdest 416 } 417 } 418} 419