1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16package xiangshan.backend.rename 17 18import chipsalliance.rocketchip.config.Parameters 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22 23class RatReadPort(implicit p: Parameters) extends XSBundle { 24 val addr = Input(UInt(5.W)) 25 val rdata = Output(UInt(PhyRegIdxWidth.W)) 26} 27 28class RatWritePort(implicit p: Parameters) extends XSBundle { 29 val wen = Input(Bool()) 30 val addr = Input(UInt(5.W)) 31 val wdata = Input(UInt(PhyRegIdxWidth.W)) 32} 33 34class RenameTable(float: Boolean)(implicit p: Parameters) extends XSModule { 35 val io = IO(new Bundle() { 36 val redirect = Input(Bool()) 37 val flush = Input(Bool()) 38 val walkWen = Input(Bool()) 39 val readPorts = Vec({if(float) 4 else 3} * RenameWidth, new RatReadPort) 40 val specWritePorts = Vec(CommitWidth, new RatWritePort) 41 val archWritePorts = Vec(CommitWidth, new RatWritePort) 42 val debug_rdata = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 43 }) 44 45 // speculative rename table 46 val spec_table = RegInit(VecInit(Seq.tabulate(32)(i => i.U(PhyRegIdxWidth.W)))) 47 48 // arch state rename table 49 val arch_table = RegInit(VecInit(Seq.tabulate(32)(i => i.U(PhyRegIdxWidth.W)))) 50 51 // When redirect happens (mis-prediction), don't update the rename table 52 // However, when mis-prediction and walk happens at the same time, rename table needs to be updated 53 for (w <- io.specWritePorts){ 54 when (w.wen && (!(io.redirect || io.flush) || io.walkWen)) { 55 spec_table(w.addr) := w.wdata 56 } 57 } 58 59 for((r, i) <- io.readPorts.zipWithIndex){ 60 r.rdata := spec_table(r.addr) 61 } 62 63 for(w <- io.archWritePorts){ 64 when(w.wen){ arch_table(w.addr) := w.wdata } 65 } 66 67 when (io.flush) { 68 spec_table := arch_table 69 // spec table needs to be updated when flushPipe 70 for (w <- io.archWritePorts) { 71 when(w.wen){ spec_table(w.addr) := w.wdata } 72 } 73 } 74 75 io.debug_rdata := arch_table 76} 77