1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility.HasCircularQueuePtrHelper 23import utility.ParallelPriorityMux 24import utility.GatedValidRegNext 25import utils.XSError 26import xiangshan._ 27 28abstract class RegType 29case object Reg_I extends RegType 30case object Reg_F extends RegType 31case object Reg_V extends RegType 32case object Reg_V0 extends RegType 33case object Reg_Vl extends RegType 34 35class RatReadPort(implicit p: Parameters) extends XSBundle { 36 val hold = Input(Bool()) 37 val addr = Input(UInt(6.W)) 38 val data = Output(UInt(PhyRegIdxWidth.W)) 39} 40 41class RatWritePort(implicit p: Parameters) extends XSBundle { 42 val wen = Bool() 43 val addr = UInt(6.W) 44 val data = UInt(PhyRegIdxWidth.W) 45} 46 47class RenameTable(reg_t: RegType)(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper { 48 49 // params alias 50 private val numVecRegSrc = backendParams.numVecRegSrc 51 private val numVecRatPorts = numVecRegSrc 52 53 val readPortsNum = reg_t match { 54 case Reg_I => 2 55 case Reg_F => 3 56 case Reg_V => 3 57 case Reg_V0 => 1 58 case Reg_Vl => 1 59 } 60 val rdataNums = reg_t match { 61 case Reg_I => 32 62 case Reg_F => 32 63 case Reg_V => 31 // no v0 64 case Reg_V0 => 1 // v0 65 case Reg_Vl => 1 // vl 66 } 67 val io = IO(new Bundle { 68 val redirect = Input(Bool()) 69 val readPorts = Vec(readPortsNum * RenameWidth, new RatReadPort) 70 val specWritePorts = Vec(RabCommitWidth, Input(new RatWritePort)) 71 val archWritePorts = Vec(RabCommitWidth, Input(new RatWritePort)) 72 val old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 73 val need_free = Vec(RabCommitWidth, Output(Bool())) 74 val snpt = Input(new SnapshotPort) 75 val diffWritePorts = if (backendParams.debugEn) Some(Vec(RabCommitWidth * MaxUopSize, Input(new RatWritePort))) else None 76 val debug_rdata = if (backendParams.debugEn) Some(Vec(rdataNums, Output(UInt(PhyRegIdxWidth.W)))) else None 77 val diff_rdata = if (backendParams.debugEn) Some(Vec(rdataNums, Output(UInt(PhyRegIdxWidth.W)))) else None 78 val debug_v0 = if (backendParams.debugEn) reg_t match { 79 case Reg_V0 => Some(Output(UInt(PhyRegIdxWidth.W))) 80 case _ => None 81 } else None 82 val diff_v0 = if (backendParams.debugEn) reg_t match { 83 case Reg_V0 => Some(Output(UInt(PhyRegIdxWidth.W))) 84 case _ => None 85 } else None 86 val debug_vl = if (backendParams.debugEn) reg_t match { 87 case Reg_Vl => Some(Output(UInt(PhyRegIdxWidth.W))) 88 case _ => None 89 } else None 90 val diff_vl = if (backendParams.debugEn) reg_t match { 91 case Reg_Vl => Some(Output(UInt(PhyRegIdxWidth.W))) 92 case _ => None 93 } else None 94 }) 95 96 // speculative rename table 97 val rename_table_init = reg_t match { 98 case Reg_I => VecInit.fill (IntLogicRegs)(0.U(PhyRegIdxWidth.W)) 99 case Reg_F => VecInit.tabulate(FpLogicRegs)(_.U(PhyRegIdxWidth.W)) 100 case Reg_V => VecInit.tabulate(VecLogicRegs)(_.U(PhyRegIdxWidth.W)) 101 case Reg_V0 => VecInit.tabulate(V0LogicRegs)(_.U(PhyRegIdxWidth.W)) 102 case Reg_Vl => VecInit.tabulate(VlLogicRegs)(_.U(PhyRegIdxWidth.W)) 103 } 104 val spec_table = RegInit(rename_table_init) 105 val spec_table_next = WireInit(spec_table) 106 // arch state rename table 107 val arch_table = RegInit(rename_table_init) 108 val arch_table_next = WireDefault(arch_table) 109 // old_pdest 110 val old_pdest = RegInit(VecInit.fill(RabCommitWidth)(0.U(PhyRegIdxWidth.W))) 111 val need_free = RegInit(VecInit.fill(RabCommitWidth)(false.B)) 112 113 // For better timing, we optimize reading and writing to RenameTable as follows: 114 // (1) Writing at T0 will be actually processed at T1. 115 // (2) Reading is synchronous now. 116 // (3) RAddr at T0 will be used to access the table and get data at T0. 117 // (4) WData at T0 is bypassed to RData at T1. 118 val t1_redirect = GatedValidRegNext(io.redirect, false.B) 119 val t1_raddr = io.readPorts.map(p => RegEnable(p.addr, !p.hold)) 120 val t1_rdata_use_t1_raddr = VecInit(t1_raddr.map(spec_table(_))) 121 val t1_wSpec = RegNext(Mux(io.redirect, 0.U.asTypeOf(io.specWritePorts), io.specWritePorts)) 122 123 val t1_snpt = RegNext(io.snpt, 0.U.asTypeOf(io.snpt)) 124 125 val snapshots = SnapshotGenerator(spec_table, t1_snpt.snptEnq, t1_snpt.snptDeq, t1_redirect, t1_snpt.flushVec) 126 127 // WRITE: when instruction commits or walking 128 val t1_wSpec_addr = t1_wSpec.map(w => Mux(w.wen, UIntToOH(w.addr), 0.U)) 129 for ((next, i) <- spec_table_next.zipWithIndex) { 130 val matchVec = t1_wSpec_addr.map(w => w(i)) 131 val wMatch = ParallelPriorityMux(matchVec.reverse, t1_wSpec.map(_.data).reverse) 132 // When there's a flush, we use arch_table to update spec_table. 133 next := Mux( 134 t1_redirect, 135 Mux(t1_snpt.useSnpt, snapshots(t1_snpt.snptSelect)(i), arch_table(i)), 136 Mux(VecInit(matchVec).asUInt.orR, wMatch, spec_table(i)) 137 ) 138 } 139 spec_table := spec_table_next 140 141 // READ: decode-rename stage 142 for ((r, i) <- io.readPorts.zipWithIndex) { 143 val t0_bypass = io.specWritePorts.map(w => w.wen && Mux(r.hold, w.addr === t1_raddr(i), w.addr === r.addr)) 144 val t1_bypass = RegNext(Mux(io.redirect, 0.U.asTypeOf(VecInit(t0_bypass)), VecInit(t0_bypass))) 145 val bypass_data = ParallelPriorityMux(t1_bypass.reverse, t1_wSpec.map(_.data).reverse) 146 r.data := Mux(t1_bypass.asUInt.orR, bypass_data, t1_rdata_use_t1_raddr(i)) 147 } 148 149 for ((w, i) <- io.archWritePorts.zipWithIndex) { 150 when (w.wen) { 151 arch_table_next(w.addr) := w.data 152 } 153 val arch_mask = VecInit.fill(PhyRegIdxWidth)(w.wen).asUInt 154 old_pdest(i) := 155 MuxCase(arch_table(w.addr) & arch_mask, 156 io.archWritePorts.take(i).reverse.map(x => (x.wen && x.addr === w.addr, x.data & arch_mask))) 157 } 158 arch_table := arch_table_next 159 160 for (((old, free), i) <- (old_pdest zip need_free).zipWithIndex) { 161 val hasDuplicate = old_pdest.take(i).map(_ === old) 162 val blockedByDup = if (i == 0) false.B else VecInit(hasDuplicate).asUInt.orR 163 free := VecInit(arch_table.map(_ =/= old)).asUInt.andR && !blockedByDup 164 } 165 166 io.old_pdest := old_pdest 167 io.need_free := need_free 168 io.debug_rdata.foreach{ x => reg_t match { 169 case Reg_V => x := arch_table.drop(1).take(rdataNums) 170 case _ => x := arch_table.take(rdataNums) 171 } 172 } 173 io.debug_v0.foreach(_ := arch_table(0)) 174 io.debug_vl.foreach(_ := arch_table(0)) 175 if (env.EnableDifftest || env.AlwaysBasicDiff) { 176 val difftest_table = RegInit(rename_table_init) 177 val difftest_table_next = WireDefault(difftest_table) 178 179 for (w <- io.diffWritePorts.get) { 180 when(w.wen) { 181 difftest_table_next(w.addr) := w.data 182 } 183 } 184 difftest_table := difftest_table_next 185 186 io.diff_rdata.foreach{ x => reg_t match { 187 case Reg_V => x := difftest_table.drop(1).take(rdataNums) 188 case _ => x := difftest_table.take(rdataNums) 189 } 190 } 191 io.diff_v0.foreach(_ := difftest_table(0)) 192 io.diff_vl.foreach(_ := difftest_table(0)) 193 } 194 else { 195 io.diff_rdata.foreach(_ := 0.U.asTypeOf(io.debug_rdata.get)) 196 io.diff_v0.foreach(_ := 0.U) 197 io.diff_vl.foreach(_ := 0.U) 198 } 199} 200 201class RenameTableWrapper(implicit p: Parameters) extends XSModule { 202 203 // params alias 204 private val numVecRegSrc = backendParams.numVecRegSrc 205 private val numVecRatPorts = numVecRegSrc 206 207 val io = IO(new Bundle() { 208 val redirect = Input(Bool()) 209 val rabCommits = Input(new RabCommitIO) 210 val diffCommits = if (backendParams.debugEn) Some(Input(new DiffCommitIO)) else None 211 val intReadPorts = Vec(RenameWidth, Vec(2, new RatReadPort)) 212 val intRenamePorts = Vec(RenameWidth, Input(new RatWritePort)) 213 val fpReadPorts = Vec(RenameWidth, Vec(3, new RatReadPort)) 214 val fpRenamePorts = Vec(RenameWidth, Input(new RatWritePort)) 215 val vecReadPorts = Vec(RenameWidth, Vec(numVecRatPorts, new RatReadPort)) 216 val vecRenamePorts = Vec(RenameWidth, Input(new RatWritePort)) 217 val v0ReadPorts = Vec(RenameWidth, new RatReadPort) 218 val v0RenamePorts = Vec(RenameWidth, Input(new RatWritePort)) 219 val vlReadPorts = Vec(RenameWidth, new RatReadPort) 220 val vlRenamePorts = Vec(RenameWidth, Input(new RatWritePort)) 221 222 val int_old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 223 val fp_old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 224 val vec_old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 225 val v0_old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 226 val vl_old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 227 val int_need_free = Vec(RabCommitWidth, Output(Bool())) 228 val snpt = Input(new SnapshotPort) 229 230 // for debug printing 231 val debug_int_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 232 val debug_fp_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 233 val debug_vec_rat = if (backendParams.debugEn) Some(Vec(31, Output(UInt(PhyRegIdxWidth.W)))) else None 234 val debug_v0_rat = if (backendParams.debugEn) Some(Vec(1,Output(UInt(PhyRegIdxWidth.W)))) else None 235 val debug_vl_rat = if (backendParams.debugEn) Some(Vec(1,Output(UInt(PhyRegIdxWidth.W)))) else None 236 237 val diff_int_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 238 val diff_fp_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 239 val diff_vec_rat = if (backendParams.debugEn) Some(Vec(31, Output(UInt(PhyRegIdxWidth.W)))) else None 240 val diff_v0_rat = if (backendParams.debugEn) Some(Vec(1,Output(UInt(PhyRegIdxWidth.W)))) else None 241 val diff_vl_rat = if (backendParams.debugEn) Some(Vec(1,Output(UInt(PhyRegIdxWidth.W)))) else None 242 }) 243 244 val intRat = Module(new RenameTable(Reg_I)) 245 val fpRat = Module(new RenameTable(Reg_F)) 246 val vecRat = Module(new RenameTable(Reg_V)) 247 val v0Rat = Module(new RenameTable(Reg_V0)) 248 val vlRat = Module(new RenameTable(Reg_Vl)) 249 250 io.debug_int_rat .foreach(_ := intRat.io.debug_rdata.get) 251 io.diff_int_rat .foreach(_ := intRat.io.diff_rdata.get) 252 intRat.io.readPorts <> io.intReadPorts.flatten 253 intRat.io.redirect := io.redirect 254 intRat.io.snpt := io.snpt 255 io.int_old_pdest := intRat.io.old_pdest 256 io.int_need_free := intRat.io.need_free 257 val intDestValid = io.rabCommits.info.map(_.rfWen) 258 for ((arch, i) <- intRat.io.archWritePorts.zipWithIndex) { 259 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && intDestValid(i) 260 arch.addr := io.rabCommits.info(i).ldest 261 arch.data := io.rabCommits.info(i).pdest 262 XSError(arch.wen && arch.addr === 0.U && arch.data =/= 0.U, "pdest for $0 should be 0\n") 263 } 264 for ((spec, i) <- intRat.io.specWritePorts.zipWithIndex) { 265 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && intDestValid(i) 266 spec.addr := io.rabCommits.info(i).ldest 267 spec.data := io.rabCommits.info(i).pdest 268 XSError(spec.wen && spec.addr === 0.U && spec.data =/= 0.U, "pdest for $0 should be 0\n") 269 } 270 for ((spec, rename) <- intRat.io.specWritePorts.zip(io.intRenamePorts)) { 271 when (rename.wen) { 272 spec.wen := true.B 273 spec.addr := rename.addr 274 spec.data := rename.data 275 } 276 } 277 if (backendParams.debugEn) { 278 for ((diff, i) <- intRat.io.diffWritePorts.get.zipWithIndex) { 279 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).rfWen 280 diff.addr := io.diffCommits.get.info(i).ldest 281 diff.data := io.diffCommits.get.info(i).pdest 282 } 283 } 284 285 // debug read ports for difftest 286 io.debug_fp_rat.foreach(_ := fpRat.io.debug_rdata.get) 287 io.diff_fp_rat .foreach(_ := fpRat.io.diff_rdata.get) 288 fpRat.io.readPorts <> io.fpReadPorts.flatten 289 fpRat.io.redirect := io.redirect 290 fpRat.io.snpt := io.snpt 291 io.fp_old_pdest := fpRat.io.old_pdest 292 293 for ((arch, i) <- fpRat.io.archWritePorts.zipWithIndex) { 294 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && io.rabCommits.info(i).fpWen 295 arch.addr := io.rabCommits.info(i).ldest 296 arch.data := io.rabCommits.info(i).pdest 297 } 298 for ((spec, i) <- fpRat.io.specWritePorts.zipWithIndex) { 299 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && io.rabCommits.info(i).fpWen 300 spec.addr := io.rabCommits.info(i).ldest 301 spec.data := io.rabCommits.info(i).pdest 302 } 303 for ((spec, rename) <- fpRat.io.specWritePorts.zip(io.fpRenamePorts)) { 304 when (rename.wen) { 305 spec.wen := true.B 306 spec.addr := rename.addr 307 spec.data := rename.data 308 } 309 } 310 if (backendParams.debugEn) { 311 for ((diff, i) <- fpRat.io.diffWritePorts.get.zipWithIndex) { 312 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).fpWen 313 diff.addr := io.diffCommits.get.info(i).ldest 314 diff.data := io.diffCommits.get.info(i).pdest 315 } 316 } 317 318 // debug read ports for difftest 319 io.debug_vec_rat .foreach(_ := vecRat.io.debug_rdata.get) 320 io.diff_vec_rat .foreach(_ := vecRat.io.diff_rdata.get) 321 vecRat.io.readPorts <> io.vecReadPorts.flatten 322 vecRat.io.redirect := io.redirect 323 vecRat.io.snpt := io.snpt 324 io.vec_old_pdest := vecRat.io.old_pdest 325 326 //TODO: RM the donTouch 327 if(backendParams.debugEn) { 328 dontTouch(vecRat.io) 329 } 330 for ((arch, i) <- vecRat.io.archWritePorts.zipWithIndex) { 331 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && io.rabCommits.info(i).vecWen 332 arch.addr := io.rabCommits.info(i).ldest 333 arch.data := io.rabCommits.info(i).pdest 334 } 335 for ((spec, i) <- vecRat.io.specWritePorts.zipWithIndex) { 336 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && io.rabCommits.info(i).vecWen 337 spec.addr := io.rabCommits.info(i).ldest 338 spec.data := io.rabCommits.info(i).pdest 339 } 340 for ((spec, rename) <- vecRat.io.specWritePorts.zip(io.vecRenamePorts)) { 341 when (rename.wen) { 342 spec.wen := true.B 343 spec.addr := rename.addr 344 spec.data := rename.data 345 } 346 } 347 if (backendParams.debugEn) { 348 for ((diff, i) <- vecRat.io.diffWritePorts.get.zipWithIndex) { 349 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).vecWen 350 diff.addr := io.diffCommits.get.info(i).ldest 351 diff.data := io.diffCommits.get.info(i).pdest 352 } 353 } 354 355 // debug read ports for difftest 356 io.debug_v0_rat.foreach(_ := v0Rat.io.debug_rdata.get) 357 io.diff_v0_rat.foreach(_ := v0Rat.io.diff_rdata.get) 358 v0Rat.io.readPorts <> io.v0ReadPorts 359 v0Rat.io.redirect := io.redirect 360 v0Rat.io.snpt := io.snpt 361 io.v0_old_pdest := v0Rat.io.old_pdest 362 363 if (backendParams.debugEn) { 364 dontTouch(v0Rat.io) 365 } 366 for ((arch, i) <- v0Rat.io.archWritePorts.zipWithIndex) { 367 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && io.rabCommits.info(i).v0Wen 368 arch.addr := io.rabCommits.info(i).ldest 369 arch.data := io.rabCommits.info(i).pdest 370 } 371 for ((spec, i) <- v0Rat.io.specWritePorts.zipWithIndex) { 372 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && io.rabCommits.info(i).v0Wen 373 spec.addr := io.rabCommits.info(i).ldest 374 spec.data := io.rabCommits.info(i).pdest 375 } 376 for ((spec, rename) <- v0Rat.io.specWritePorts.zip(io.v0RenamePorts)) { 377 when(rename.wen) { 378 spec.wen := true.B 379 spec.addr := rename.addr 380 spec.data := rename.data 381 } 382 } 383 if (backendParams.debugEn) { 384 for ((diff, i) <- v0Rat.io.diffWritePorts.get.zipWithIndex) { 385 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).v0Wen 386 diff.addr := io.diffCommits.get.info(i).ldest 387 diff.data := io.diffCommits.get.info(i).pdest 388 } 389 } 390 391 // debug read ports for difftest 392 io.debug_vl_rat.foreach(_ := vlRat.io.debug_rdata.get) 393 io.diff_vl_rat.foreach(_ := vlRat.io.diff_rdata.get) 394 vlRat.io.readPorts <> io.vlReadPorts 395 vlRat.io.redirect := io.redirect 396 vlRat.io.snpt := io.snpt 397 io.vl_old_pdest := vlRat.io.old_pdest 398 399 if (backendParams.debugEn) { 400 dontTouch(vlRat.io) 401 } 402 for ((arch, i) <- vlRat.io.archWritePorts.zipWithIndex) { 403 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && io.rabCommits.info(i).vlWen 404 arch.addr := io.rabCommits.info(i).ldest 405 arch.data := io.rabCommits.info(i).pdest 406 } 407 for ((spec, i) <- vlRat.io.specWritePorts.zipWithIndex) { 408 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && io.rabCommits.info(i).vlWen 409 spec.addr := io.rabCommits.info(i).ldest 410 spec.data := io.rabCommits.info(i).pdest 411 } 412 for ((spec, rename) <- vlRat.io.specWritePorts.zip(io.vlRenamePorts)) { 413 when(rename.wen) { 414 spec.wen := true.B 415 spec.addr := rename.addr 416 spec.data := rename.data 417 } 418 } 419 if (backendParams.debugEn) { 420 for ((diff, i) <- vlRat.io.diffWritePorts.get.zipWithIndex) { 421 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).vlWen 422 diff.addr := io.diffCommits.get.info(i).ldest 423 diff.data := io.diffCommits.get.info(i).pdest 424 } 425 } 426} 427