xref: /XiangShan/src/test/scala/top/SimMMIO.scala (revision bbe4506dea963b9c4bf6379d789e413ba6647955) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chisel3._
20import org.chipsalliance.cde.config.Parameters
21import device._
22import freechips.rocketchip.amba.axi4.{AXI4EdgeParameters, AXI4MasterNode, AXI4Xbar}
23import freechips.rocketchip.diplomacy.{AddressSet, InModuleBody, LazyModule, LazyModuleImp}
24import difftest._
25import utility.AXI4Error
26import system.{HasPeripheralRanges, HasSoCParameter}
27
28class SimMMIO(edge: AXI4EdgeParameters)(implicit p: Parameters) extends LazyModule
29  with HasSoCParameter
30  with HasPeripheralRanges
31{
32
33  val node = AXI4MasterNode(List(edge.master))
34
35  // val uartRange = AddressSet(0x40600000, 0x3f) // ?
36  val flashRange = AddressSet(0x10000000L, 0xfffffff)
37  val sdRange = AddressSet(0x40002000L, 0xfff)
38  val intrGenRange = AddressSet(0x40070000L, 0x0000ffffL)
39
40  val illegalRange = (onChipPeripheralRanges.values ++ Seq(
41    soc.UARTLiteRange,
42    flashRange,
43    sdRange,
44    intrGenRange
45  )).foldLeft(Seq(AddressSet(0x0, 0x7fffffffL)))((acc, x) => acc.flatMap(_.subtract(x)))
46
47  val flash = LazyModule(new AXI4Flash(Seq(AddressSet(0x10000000L, 0xfffffff))))
48  val uart = LazyModule(new AXI4UART(Seq(soc.UARTLiteRange)))
49  // val vga = LazyModule(new AXI4VGA(
50  //   sim = false,
51  //   fbAddress = Seq(AddressSet(0x50000000L, 0x3fffffL)),
52  //   ctrlAddress = Seq(AddressSet(0x40001000L, 0x7L))
53  // ))
54  val sd = LazyModule(new AXI4DummySD(Seq(AddressSet(0x40002000L, 0xfff))))
55  val intrGen = LazyModule(new AXI4IntrGenerator(Seq(AddressSet(0x40070000L, 0x0000ffffL))))
56  val error = LazyModule(new AXI4Error(illegalRange))
57
58  val axiBus = AXI4Xbar()
59
60  uart.node := axiBus
61  // vga.node :*= axiBus
62  flash.node := axiBus
63  sd.node := axiBus
64  intrGen.node := axiBus
65  error.node := axiBus
66
67  axiBus := node
68
69  val io_axi4 = InModuleBody {
70    node.makeIOs()
71  }
72
73  class SimMMIOImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
74    val io = IO(new Bundle() {
75      val uart = new UARTIO
76      val interrupt = new IntrGenIO
77    })
78    io.uart <> uart.module.io.extra.get
79    io.interrupt <> intrGen.module.io.extra.get
80  }
81
82  lazy val module = new SimMMIOImp(this)
83}
84