fix(MMIO): use fine-grained on-chip MMIO ranges (#3730)

Previously, on-chip devices use a continuous memory range, which
contains many memory holes not actually used. If we access these holes,
the

fix(MMIO): use fine-grained on-chip MMIO ranges (#3730)

Previously, on-chip devices use a continuous memory range, which
contains many memory holes not actually used. If we access these holes,
the core will hang. This commit use fine-grained on-chip MMIO ranges so
that memory accessing of these holes will be routed out of core and
handled by other mechanisms.

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SimMMIO: add AXI4Error to handle void address space

Bump rocket-chip (#2353)

chore: remove deprecated brackets, APIs, etc. (#2321)

sim,mmio: remove the vga device (#1638)

The VGA device may cause assertions in AXI4SlaveModule because it
may send arbitrary requests to fb (AXI4RAM).

Refactor top (#1093)

* Temporarily disable TLMonitor

* Bump huancun (L2/L3 MSHR bug fix)

* Refactor Top

* Bump huancun

* alu: fix bug of rev8 & orc.b instruction

Co-authored-by: Zhang

Refactor top (#1093)

* Temporarily disable TLMonitor

* Bump huancun (L2/L3 MSHR bug fix)

* Refactor Top

* Bump huancun

* alu: fix bug of rev8 & orc.b instruction

Co-authored-by: Zhangfw <[email protected]>

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Update difftest to use NEMU master branch (#902)

misc: implement difftest as a submodule

misc: update PCL information (#899)

XiangShan is jointly released by ICT and PCL.

Add MulanPSL-2.0 License (#824)

In this commit, we add License for XiangShan project.

device: add AXI4IntrGenerator to generate external interrupts (#819)

This commit adds a new AXI4 device to generate external interrupts.
Previously none of the simulated external devices trigger in

device: add AXI4IntrGenerator to generate external interrupts (#819)

This commit adds a new AXI4 device to generate external interrupts.
Previously none of the simulated external devices trigger interrupts.
To test external interrupts, we add this device.

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Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's

Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr.
(2) DPI-C is cross-platform (Verilator, VCS, ...)
(3) difftest APIs are splited from emu.cpp to possibly support more backend platforms
(NEMU, Spike, ...)

The performance at this commit is quite slower than the original emu.
Performance issues will be fixed later.

* [WIP] SimTop: try to use 'XSTop' as soc

* CircularQueuePtr: ues F-bounded polymorphis instead implict helper

* Refactor parameters & Clean up code

* difftest: support basic difftest

* Support diffetst in new sim top

* Difftest; convert recode fmt to ieee754 when comparing fp regs

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Debug: add int/exc inst wb to debug queue

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Difftest: fix naive commit num limit

Co-authored-by: Yinan Xu <[email protected]>
Co-authored-by: William Wang <[email protected]>

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Update SoC and verilog generation for FPGA/ASIC platform (#653)

* MySoc: verilog top

* MySoc: connect mmio

* MySoc: fix some bugs

* wip

* TopMain: remove to top

* WIP: add dma port

Update SoC and verilog generation for FPGA/ASIC platform (#653)

* MySoc: verilog top

* MySoc: connect mmio

* MySoc: fix some bugs

* wip

* TopMain: remove to top

* WIP: add dma port

* Update XSTop for FPGA/ASIC platform

* Top: add rocket-chip source

* Append SRAM to generated verilog

Co-authored-by: LinJiawei <[email protected]>

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MMIO: change flash address to 0x10000000

AXI4SlaveModule: use Seq[AddressSet] instead of AddressSet
to allow more flexible address range configuration.
With only one AddressSet, we can not even represent
very simple address ranges like [2G,

AXI4SlaveModule: use Seq[AddressSet] instead of AddressSet
to allow more flexible address range configuration.
With only one AddressSet, we can not even represent
very simple address ranges like [2G, 32G).

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diplomacy soc finish, use dummy core now

Rewrite SimMMIO

MMIOTLToAXI4: add a TL to AXI4 converter for MMIO.

SOC: move to tilelink, remove simple bus

Merge master into dev-fronend

Adapt device address

system,SoC: clean up external CLINT

system,SoC: move CLINT into SoC

device: add AXI4DummySD

device: add flash to jump to dram

device,AXI4Timer: make the register offset match standard CLINT