xref: /XiangShan/src/test/scala/top/SimMMIO.scala (revision 4bf9a9786a26f6ac8c9e7a902e22fe3ac746c55a) 
1package top
2
3import chisel3._
4import chisel3.util._
5
6import bus.simplebus._
7import device._
8
9class SimMMIO extends Module {
10  val io = IO(new Bundle {
11    val rw = Flipped(new SimpleBusUC)
12    val mtip = Output(Bool())
13  })
14
15  val devAddrSpace = List(
16    (0x40600000L, 0x10L), // uart
17    (0x40700000L, 0x10000L), // timer
18    (0x41000000L, 0x400000L), // vmem
19    (0x40800000L, 0x8L),  // vga ctrl
20    (0x40000000L, 0x1000L),  // flash
21    (0x40002000L, 0x1000L)  // dummy sdcard
22  )
23
24  val xbar = Module(new SimpleBusCrossbar1toN(devAddrSpace))
25  xbar.io.in <> io.rw
26
27  val uart = Module(new AXI4UART)
28  val timer = Module(new AXI4Timer(sim = true))
29  val vga = Module(new AXI4VGA(sim = true))
30  val flash = Module(new AXI4Flash)
31  val sd = Module(new AXI4DummySD)
32  uart.io.in <> xbar.io.out(0).toAXI4Lite()
33  timer.io.in <> xbar.io.out(1).toAXI4Lite()
34  vga.io.in.fb <> xbar.io.out(2).toAXI4Lite()
35  vga.io.in.ctrl <> xbar.io.out(3).toAXI4Lite()
36  flash.io.in <> xbar.io.out(4).toAXI4Lite()
37  sd.io.in <> xbar.io.out(5).toAXI4Lite()
38  vga.io.vga := DontCare
39
40  io.mtip := timer.io.extra.get.mtip
41}
42