xref: /XiangShan/src/test/scala/top/SimMMIO.scala (revision 5a7b942b030b799f8086bf9a6096981200fb8b46) 
1package top
2
3import chisel3._
4import chisel3.util._
5
6import bus.simplebus.SimpleBus
7
8class SimMMIO extends Module {
9  val io = IO(new Bundle {
10    val rw = Flipped(new SimpleBus)
11    val mmioTrap = new Bundle {
12      val valid = Output(Bool())
13      val cmd = Output(UInt(3.W))
14      val rdata = Input(UInt(32.W))
15    }
16  })
17
18  val wen = io.rw.isWrite()
19  val wdataVec = VecInit.tabulate(4) { i => io.rw.req.bits.wdata(8 * (i + 1) - 1, 8 * i) }
20  val wmask = VecInit.tabulate(4) { i => io.rw.req.bits.wmask(i).toBool }
21
22  io.mmioTrap.valid := false.B
23  io.mmioTrap.cmd := 0.U
24
25  when (io.rw.req.valid) {
26    switch (io.rw.req.bits.addr) {
27      is (0x40600008.U) {
28        // read uartlite stat register
29        io.mmioTrap.valid := true.B
30        io.mmioTrap.cmd := 0.U
31      }
32      is (0x4060000c.U) {
33        // read uartlite ctrl register
34        io.mmioTrap.valid := true.B
35        io.mmioTrap.cmd := 0.U
36      }
37      is (0x40600004.U) {
38        io.mmioTrap.valid := true.B
39        io.mmioTrap.cmd := 6.U
40        when (wen) { printf("%c", wdataVec(0)) }
41      }
42      is (0x40700000.U) {
43        // read RTC
44        io.mmioTrap.valid := true.B
45        io.mmioTrap.cmd := 1.U
46      }
47      is (0x40900000.U) {
48        // read key
49        io.mmioTrap.valid := true.B
50        io.mmioTrap.cmd := 2.U
51      }
52      is (0x40800000.U) {
53        // read screen size
54        io.mmioTrap.valid := true.B
55        io.mmioTrap.cmd := 3.U
56      }
57      is (0x40800004.U) {
58        // write vga sync
59        io.mmioTrap.valid := true.B
60        io.mmioTrap.cmd := 4.U
61      }
62    }
63
64    when (io.rw.req.bits.addr >= 0x40000000.U && io.rw.req.bits.addr < 0x40400000.U && wen) {
65      // write to vmem
66      io.mmioTrap.valid := true.B
67      io.mmioTrap.cmd := 5.U
68    }
69  }
70
71  io.rw.req.ready := true.B
72  io.rw.resp.bits.rdata := io.mmioTrap.rdata
73  io.rw.resp.valid := io.mmioTrap.valid
74
75  assert(!io.rw.req.valid || io.mmioTrap.valid, "bad addr = 0x%x", io.rw.req.bits.addr)
76}
77