1package top 2 3import chisel3._ 4import chisel3.util._ 5 6import memory.MemIO 7 8class SimMMIO extends Module { 9 val io = IO(new Bundle { 10 val rw = Flipped(new MemIO) 11 val mmioTrap = new Bundle { 12 val valid = Output(Bool()) 13 val cmd = Output(UInt(3.W)) 14 val rdata = Input(UInt(32.W)) 15 } 16 }) 17 18 val wen = io.rw.a.valid && io.rw.w.valid 19 val wdataVec = VecInit.tabulate(4) { i => io.rw.w.bits.data(8 * (i + 1) - 1, 8 * i) } 20 val wmask = VecInit.tabulate(4) { i => io.rw.w.bits.mask(i).toBool } 21 22 io.mmioTrap.valid := false.B 23 io.mmioTrap.cmd := 0.U 24 25 when (io.rw.a.valid) { 26 switch (io.rw.a.bits.addr) { 27 is (0x43f8.U) { 28 io.mmioTrap.valid := true.B 29 io.mmioTrap.cmd := 6.U 30 when (wen) { printf("%c", wdataVec(0)) } 31 } 32 is (0x4048.U) { 33 // read RTC 34 io.mmioTrap.valid := true.B 35 io.mmioTrap.cmd := 0.U 36 } 37 is (0x4060.U) { 38 // read key 39 io.mmioTrap.valid := true.B 40 io.mmioTrap.cmd := 1.U 41 } 42 is (0x4100.U) { 43 // read screen size 44 io.mmioTrap.valid := true.B 45 io.mmioTrap.cmd := 2.U 46 } 47 is (0x4104.U) { 48 // write vga sync 49 io.mmioTrap.valid := true.B 50 io.mmioTrap.cmd := 4.U 51 } 52 } 53 54 when (io.rw.a.bits.addr >= 0x40000.U && io.rw.a.bits.addr < 0xc0000.U && wen) { 55 // write to vmem 56 io.mmioTrap.valid := true.B 57 io.mmioTrap.cmd := 5.U 58 } 59 } 60 61 io.rw.a.ready := true.B 62 io.rw.r.bits.data := io.mmioTrap.rdata 63 io.rw.r.valid := io.mmioTrap.valid 64} 65