1package top 2 3import chisel3._ 4import chisel3.util._ 5 6import bus.simplebus._ 7import device._ 8 9class SimMMIO extends Module { 10 val io = IO(new Bundle { 11 val rw = Flipped(new SimpleBusUC) 12 }) 13 14 val devAddrSpace = List( 15 (0x40600000L, 0x10L), // uart 16 (0x50000000L, 0x400000L), // vmem 17 (0x40001000L, 0x8L), // vga ctrl 18 (0x40000000L, 0x1000L), // flash 19 (0x40002000L, 0x1000L) // dummy sdcard 20 ) 21 22 val xbar = Module(new SimpleBusCrossbar1toN(devAddrSpace)) 23 xbar.io.in <> io.rw 24 25 val uart = Module(new AXI4UART) 26 val vga = Module(new AXI4VGA(sim = true)) 27 val flash = Module(new AXI4Flash) 28 val sd = Module(new AXI4DummySD) 29 uart.io.in <> xbar.io.out(0).toAXI4Lite() 30 vga.io.in.fb <> xbar.io.out(1).toAXI4Lite() 31 vga.io.in.ctrl <> xbar.io.out(2).toAXI4Lite() 32 flash.io.in <> xbar.io.out(3).toAXI4Lite() 33 sd.io.in <> xbar.io.out(4).toAXI4Lite() 34 vga.io.vga := DontCare 35} 36