xref: /XiangShan/src/test/scala/top/SimTop.scala (revision d4aca96cccdcdafa80dd344996e18d1978a01af7) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chipsalliance.rocketchip.config.{Config, Parameters}
20import chisel3.stage.ChiselGeneratorAnnotation
21import chisel3._
22
23import device.{AXI4RAMWrapper, SimJTAG}
24import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
25import utils.GTimer
26import xiangshan.{DebugOptions, DebugOptionsKey}
27import chipsalliance.rocketchip.config._
28import freechips.rocketchip.devices.debug._
29import difftest._
30
31class SimTop(implicit p: Parameters) extends Module {
32  val debugOpts = p(DebugOptionsKey)
33  val useDRAMSim = debugOpts.UseDRAMSim
34
35  val l_soc = LazyModule(new XSTopWithoutDMA())
36  val soc = Module(l_soc.module)
37
38  val l_simMMIO = LazyModule(new SimMMIO(l_soc.peripheralNode.in.head._2))
39  val simMMIO = Module(l_simMMIO.module)
40  l_simMMIO.connectToSoC(l_soc)
41
42  if(!useDRAMSim){
43    val l_simAXIMem = LazyModule(new AXI4RAMWrapper(
44      l_soc.memAXI4SlaveNode, 8L * 1024 * 1024 * 1024, useBlackBox = true
45    ))
46    val simAXIMem = Module(l_simAXIMem.module)
47    l_simAXIMem.connectToSoC(l_soc)
48  }
49
50  soc.io.clock := clock.asBool()
51  soc.io.reset := reset.asBool()
52  soc.io.extIntrs := simMMIO.io.interrupt.intrVec
53
54  val success = Wire(Bool())
55  val jtag = Module(new SimJTAG(tickDelay=3)(p)).connect(soc.io.systemjtag.jtag, clock, reset.asBool, ~reset.asBool, success)
56  soc.io.systemjtag.reset := reset
57  soc.io.systemjtag.mfr_id := 0.U(11.W)
58  soc.io.systemjtag.part_number := 0.U(16.W)
59  soc.io.systemjtag.version := 0.U(4.W)
60
61  val io = IO(new Bundle(){
62    val logCtrl = new LogCtrlIO
63    val perfInfo = new PerfInfoIO
64    val uart = new UARTIO
65    val memAXI = if(useDRAMSim) l_soc.memory.cloneType else null
66  })
67
68  simMMIO.io.uart <> io.uart
69
70  if(useDRAMSim){
71    io.memAXI <> l_soc.memory
72  }
73
74  if (debugOpts.EnableDebug || debugOpts.EnablePerfDebug) {
75    val timer = GTimer()
76    val logEnable = (timer >= io.logCtrl.log_begin) && (timer < io.logCtrl.log_end)
77    ExcitingUtils.addSource(logEnable, "DISPLAY_LOG_ENABLE")
78    ExcitingUtils.addSource(timer, "logTimestamp")
79  }
80
81  if (debugOpts.EnablePerfDebug) {
82    val clean = io.perfInfo.clean
83    val dump = io.perfInfo.dump
84    ExcitingUtils.addSource(clean, "XSPERF_CLEAN")
85    ExcitingUtils.addSource(dump, "XSPERF_DUMP")
86  }
87
88  // Check and dispaly all source and sink connections
89  ExcitingUtils.fixConnections()
90  ExcitingUtils.checkAndDisplay()
91}
92
93object SimTop extends App {
94
95  override def main(args: Array[String]): Unit = {
96    val (config, firrtlOpts) = ArgParser.parse(args, fpga = false)
97    // generate verilog
98    XiangShanStage.execute(
99      firrtlOpts,
100      Seq(
101        ChiselGeneratorAnnotation(() => new SimTop()(config))
102      )
103    )
104  }
105}
106