1package xiangshan 2 3import chisel3._ 4import chisel3.stage._ 5import chiseltest._ 6import chiseltest.ChiselScalatestTester 7import chiseltest.VerilatorBackendAnnotation 8import chiseltest.simulator.{VerilatorCFlags, VerilatorFlags} 9import freechips.rocketchip.util.HasRocketChipStageUtils 10import org.scalatest.flatspec.AnyFlatSpec 11import org.scalatest.matchers.must.Matchers 12import firrtl.stage.RunFirrtlTransformAnnotation 13import xstransforms.PrintModuleName 14import firrtl.options.TargetDirAnnotation 15import top.ArgParser 16import utility.FileRegisters 17import xiangshan.backend.decode.DecodeUnit 18import xiangshan.backend.regfile.IntPregParams 19 20object DecodeMain extends App with HasRocketChipStageUtils { 21 override def main(args: Array[String]): Unit = { 22 val (config, firrtlOpts, firrtlComplier, firtoolOpts) = ArgParser.parse(args) 23 // //val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config) 24 // If Complex Params are needed, wrap it with a Top Module to do dirty works, 25 // and use "chisel3.aop.Select.collectDeep[ModuleWanted](WrapperModule){case a: ModuleWanted => a}.head.Params" 26 val defaultConfig = config.alterPartial({ 27 // Get XSCoreParams and pass it to the "small module" 28 case XSCoreParamsKey => config(XSTileKey).head.copy( 29 // Example of how to change params 30 intPreg = IntPregParams( 31 numEntries = 64, 32 numRead = Some(14), 33 numWrite = Some(8), 34 ), 35 ) 36 }) 37 (new ChiselStage).execute(args, Seq( 38 ChiselGeneratorAnnotation(() => new DecodeUnit()(defaultConfig) 39 ))) 40// // Generate files when compiling. Used by ChiselDB. 41// FileRegisters.write("./build") 42 } 43} 44 45class DecodeUnitTest extends XSTester { 46 behavior of "DecodeUnit" 47 it should "pass" in { 48 test(new DecodeUnit()(config)).withAnnotations(Seq( 49 VerilatorBackendAnnotation, 50 VerilatorFlags(Seq()), 51 WriteVcdAnnotation, 52 TargetDirAnnotation("./build"), 53 RunFirrtlTransformAnnotation(new PrintModuleName) 54 )){ dut => 55 dut.clock.step(10) 56 } 57 } 58}