1package xiangshan 2 3import chisel3._ 4import chisel3.stage._ 5import chiseltest._ 6import chiseltest.ChiselScalatestTester 7import chiseltest.VerilatorBackendAnnotation 8import chiseltest.simulator.{VerilatorFlags, VerilatorCFlags} 9import freechips.rocketchip.util.HasRocketChipStageUtils 10import org.scalatest.flatspec.AnyFlatSpec 11import org.scalatest.matchers.must.Matchers 12import firrtl.stage.RunFirrtlTransformAnnotation 13import xstransforms.PrintModuleName 14import firrtl.options.TargetDirAnnotation 15import top.ArgParser 16import utility.FileRegisters 17import xiangshan.backend.decode.DecodeUnit 18 19object DecodeMain extends App with HasRocketChipStageUtils { 20 override def main(args: Array[String]): Unit = { 21 val (config, firrtlOpts, firrtlComplier, firtoolOpts) = ArgParser.parse(args) 22 // //val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config) 23 // If Complex Params are needed, wrap it with a Top Module to do dirty works, 24 // and use "chisel3.aop.Select.collectDeep[ModuleWanted](WrapperModule){case a: ModuleWanted => a}.head.Params" 25 val defaultConfig = config.alterPartial({ 26 // Get XSCoreParams and pass it to the "small module" 27 case XSCoreParamsKey => config(XSTileKey).head.copy( 28 // Example of how to change params 29 IssQueSize = 12 30 ) 31 }) 32 (new ChiselStage).execute(args, Seq( 33 ChiselGeneratorAnnotation(() => new DecodeUnit()(defaultConfig) 34 ))) 35// // Generate files when compiling. Used by ChiselDB. 36// FileRegisters.write("./build") 37 } 38} 39 40class DecodeUnitTest extends XSTester { 41 behavior of "DecodeUnit" 42 it should "pass" in { 43 test(new DecodeUnit()(config)).withAnnotations(Seq( 44 VerilatorBackendAnnotation, 45 VerilatorFlags(Seq()), 46 WriteVcdAnnotation, 47 TargetDirAnnotation("./build"), 48 RunFirrtlTransformAnnotation(new PrintModuleName) 49 )){ dut => 50 dut.clock.step(10) 51 } 52 } 53}