Use 256-bit aligned Get and PutPartial for Debug Module System Bus Access (#1426)

Rocket's Debug Module uses unaligned Get and Put to access physical memory. However, our non-inclusive L3 does not h

Use 256-bit aligned Get and PutPartial for Debug Module System Bus Access (#1426)

Rocket's Debug Module uses unaligned Get and Put to access physical memory. However, our non-inclusive L3 does not have very good support for non-aligned Puts and Gets, so here 256-bit aligned PutPartial and Get is used.
Currently on every request, only 1 byte of data is stored using mask, and only one byte of loaded data is used, because otherwise it would require a lot more modification to Rocket's code.
Note that this feature is currently only usable with DefaultConfig.

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SoC: Buffer adjustment (#1403)

* SoC: Use TLBuffer instead TLEdgeBuffer

* Buffer adjustment

add buffer at tl pma

SoC: insert more buffers into mmio path (#1329)

* SoC: add axi4spliter

* pmp: add apply method to reduce loc

* pma: add PMA used in axi4's spliter

* Fix package import

* pma: re-write tl

SoC: insert more buffers into mmio path (#1329)

* SoC: add axi4spliter

* pmp: add apply method to reduce loc

* pma: add PMA used in axi4's spliter

* Fix package import

* pma: re-write tl-pma, put tl-pma into AXI4Spliter

* pma: add memory mapped pma

* soc: rm dma port, rm axi4spliter, mv mmpma out of spliter

* csr: clear mstatus.mprv when mstatus.mpp != ModeM at xret

* csr: fix write mask for mstatus, mepc and sepc

This commit fixes the write mask for mstatus, mepc and sepc.

According to the RISC-V instruction manual, for RV64 systems,
the SXL and UXL fields are WARL fields that control the value of
XLEN for S-mode and U-mode, respectively. For RV64 systems, if
S-mode is not supported, then SXL is hardwired to zero. For RV64
systems, if U-mode is not supported, then UXL is hardwired to zero.

Besides, mepc[0] and sepc[0] should be hardwired to zero.

* wb,load: delay load fp for one cycle

* csr: add mconfigptr, but hardwire to 0 now

* bump huancun

* csr: add *BE to mstatusStruct which are hardwired to 0

* Remove unused files

* csr: fix bug of xret clear mprv

* bump difftest

* ci: add unit test, xret clear mstatus.mprv when xpp is not M

* bump ready-to-run

* mem,atomics: delay exception info for one cycle

* SoC: insert more buffers into mmio path

* SoC: insert buffer between l3_xbar and l3_banked_xbar

* Optimze l3->ddr path

* Bump huancun

Co-authored-by: ZhangZifei <[email protected]>
Co-authored-by: Yinan Xu <[email protected]>
Co-authored-by: wangkaifan <[email protected]>

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Add pma checker for I/O device (#1300)

* SoC: add axi4spliter

* pmp: add apply method to reduce loc

* pma: add PMA used in axi4's spliter

* Fix package import

* pma: re-write tl-pma, put

Add pma checker for I/O device (#1300)

* SoC: add axi4spliter

* pmp: add apply method to reduce loc

* pma: add PMA used in axi4's spliter

* Fix package import

* pma: re-write tl-pma, put tl-pma into AXI4Spliter

* pma: add memory mapped pma

* soc: rm dma port, rm axi4spliter, mv mmpma out of spliter

* Remove unused files

* update dma pma check port at SimTop.scala; update pll lock defalt value to 1

Co-authored-by: ZhangZifei <[email protected]>
Co-authored-by: rvcoresjw <[email protected]>

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update id and dma data width (#1278)

* update id width, set io bits to do not touch
* modify dma data width from 128bits to 256 bits

Change L2 to 4 banks (#1256)

* misc: soc timing optimize

* XSTile: insert buffer between L1Dcache and L2

* Bump huancun

* Change L2 to 4 banks

* Adjust buffers

* Add more buffers for

Change L2 to 4 banks (#1256)

* misc: soc timing optimize

* XSTile: insert buffer between L1Dcache and L2

* Bump huancun

* Change L2 to 4 banks

* Adjust buffers

* Add more buffers for peripheral port

* Fix submodule version

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SoC timing fix (#1253)

* misc: soc timing optimize

* XSTile: insert buffer between L1Dcache and L2

update plic support 64 exter interrupts

update pma default value, reg 3 pipe of exter_interrupts

SoC: change buffer latency && set L3 size to 8MB (#1205)

* SoC: change buffer latency && set L3 size to 8MB

* BinaryArbiter: fix bugs when iknow < 4

top: change physical address width to 36 (#1188)

Refactor config & Add pll (#1181)

* Add cache ctrl node

* L2/L3: Reduce client dir size

* Ctrl: connect soft reset from L3 to core

* Add pll

* Config: seperate SocParams and CoreParams t

Refactor config & Add pll (#1181)

* Add cache ctrl node

* L2/L3: Reduce client dir size

* Ctrl: connect soft reset from L3 to core

* Add pll

* Config: seperate SocParams and CoreParams to get correct number of cores

* Bump huancun

* Add pll output

* Fix inclusive cache config

* Add one more pll ctrl reg

* Bump huancun

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Optimize L2->L3 crossbar (#1177)

* Bump huancun

* Simplify l2 -> l3 cross bar

* HuanCun: remove debug print

Config update (#1164)

* Bump HuanCun
* Increase L2/L3 latency
* Change 10MB L3 to default config
* Bump difftest

Refactor top (#1093)

* Temporarily disable TLMonitor

* Bump huancun (L2/L3 MSHR bug fix)

* Refactor Top

* Bump huancun

* alu: fix bug of rev8 & orc.b instruction

Co-authored-by: Zhang

Refactor top (#1093)

* Temporarily disable TLMonitor

* Bump huancun (L2/L3 MSHR bug fix)

* Refactor Top

* Bump huancun

* alu: fix bug of rev8 & orc.b instruction

Co-authored-by: Zhangfw <[email protected]>

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Refactor cache params (#1078)

Use HuanCun instead of block-inclusive-cache (#1016)

* misc: add submodule huancun

* huancun: integrate huancun to SoC as L3

* remove l2prefetcher

* update huancun

* Bump HuanCun

* Us

Use HuanCun instead of block-inclusive-cache (#1016)

* misc: add submodule huancun

* huancun: integrate huancun to SoC as L3

* remove l2prefetcher

* update huancun

* Bump HuanCun

* Use HuanCun instead old L2/L3

* bump huancun

* bump huancun

* Set L3NBanks to 4

* Update rocketchip

* Bump huancun

* Bump HuanCun

* Optimize debug configs

* Configs: fix L3 bug

* Add TLLogger

* TLLogger: fix release ack address

* Support write prefix into database

* Recoding more tilelink info

* Add a database output format converter

* missqueue: add difftest port for memory difftest during refill

* misc: bump difftest

* misc: bump difftest & huancun

* missqueue: do not check refill data when get Grant

* Add directory debug tool

* config: increase client dir size for non-inclusive cache

* Bump difftest and huancun

* Update l2/l3 cache configs

* Remove deprecated fpga/*

* Remove cache test

* Remove L2 preftecher

* bump huancun

* Params: turn on l2 prefetch by default

* misc: remove duplicate chisel-tester2

* misc: remove sifive inclusive cache

* bump difftest

* bump huancun

* config: use 4MB L3 cache

* bump huancun

* bump difftest

* bump difftest

Co-authored-by: wangkaifan <[email protected]>
Co-authored-by: TangDan <[email protected]>

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misc: update PCL information (#899)

XiangShan is jointly released by ICT and PCL.

Add MulanPSL-2.0 License (#824)

In this commit, we add License for XiangShan project.

Configs: update MinimalConfig for FPGA (#809)

* Configs: add MinimalFPGAConfig

* TODO: change cache parameters

* Chore: add parameter print

* README: add simulation usage

Currently, Xian

Configs: update MinimalConfig for FPGA (#809)

* Configs: add MinimalFPGAConfig

* TODO: change cache parameters

* Chore: add parameter print

* README: add simulation usage

Currently, XiangShan does not support NOOP FPGA. FPGA related
instructions are removed

* Configs: limit frontend width in MinimalConfig

* MinimalConfig: limit L1/L2 cache size

* MinimalConfig: limit ptw size, disable L2

* MinimalConfig: limit L3 size

* Sbuffer: force trigger write if sbuffer fulls

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Disable L2 and L3 in MinimalConfig

cache: support fake dcache, ptw, l1pluscache, l2cache and l3cache (#795)

In this commit, we add support for using DPI-C calls to replace
DCache, PTW and L1plusCache. L2Cache and L3 Cache are also a

cache: support fake dcache, ptw, l1pluscache, l2cache and l3cache (#795)

In this commit, we add support for using DPI-C calls to replace
DCache, PTW and L1plusCache. L2Cache and L3 Cache are also allowed to
be ignored or bypassed. Configurations are controlled by useFakeDCache,
useFakePTW, useFakeL1plusCache, useFakeL2Cache and useFakeL3Cache.
However, some configurations may not work correctly.

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Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's

Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr.
(2) DPI-C is cross-platform (Verilator, VCS, ...)
(3) difftest APIs are splited from emu.cpp to possibly support more backend platforms
(NEMU, Spike, ...)

The performance at this commit is quite slower than the original emu.
Performance issues will be fixed later.

* [WIP] SimTop: try to use 'XSTop' as soc

* CircularQueuePtr: ues F-bounded polymorphis instead implict helper

* Refactor parameters & Clean up code

* difftest: support basic difftest

* Support diffetst in new sim top

* Difftest; convert recode fmt to ieee754 when comparing fp regs

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Debug: add int/exc inst wb to debug queue

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Difftest: fix naive commit num limit

Co-authored-by: Yinan Xu <[email protected]>
Co-authored-by: William Wang <[email protected]>

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InclusiveCache: add fpga parameter for reset delay. (#752)