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c1254d7e |
| 23-Oct-2023 |
sfencevma <[email protected]> |
flatten issue and writeback ports
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8f1fa9b1 |
| 23-Oct-2023 |
sfencevma <[email protected]> |
add hybrid unit
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| #
b133b458 |
| 21-Oct-2023 |
Xuan Hu <[email protected]> |
backend,mem: support HybridUnit
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| #
a81cda24 |
| 19-Oct-2023 |
sfencevma <[email protected]> |
3ld2st-for-new-backend
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11ed75ef |
| 26-Oct-2023 |
Xuan Hu <[email protected]> |
backend: flipped load issue and writeback ports
* We flipped both issue and writeback ports to avoid potential error.
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e8800897 |
| 25-Oct-2023 |
Xuan Hu <[email protected]> |
backend: deq load uop when it enters memblock successfully
* This can release the oldest uop in load issue queue 3 cycles earlier than before.
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| #
7a96cc7f |
| 01-Nov-2023 |
Haojin Tang <[email protected]> |
ExuOH: use UInt instead of Vec[Bool] to reduce generating time
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4e12f40b |
| 17-Oct-2023 |
zhanglinjuan <[email protected]> |
XSTile partition (#2390)
This pull request partitions XSTile into L2Top and XSCore. L2Top contains all the modules including crossbars and CoupledL2. XSCore contains Frontend, Backend, and MemBlock
XSTile partition (#2390)
This pull request partitions XSTile into L2Top and XSCore. L2Top contains all the modules including crossbars and CoupledL2. XSCore contains Frontend, Backend, and MemBlock and all the interfaces from core to tile will go through MemBlock.
show more ...
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| #
1ca4a39d |
| 15-Oct-2023 |
Xuan Hu <[email protected]> |
backend: add shouldBeInlined = false
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| #
6ce10964 |
| 12-Oct-2023 |
Xuan Hu <[email protected]> |
fix merge errors
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| #
83ba63b3 |
| 11-Oct-2023 |
Xuan Hu <[email protected]> |
fix merge error
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| #
b0507133 |
| 06-Oct-2023 |
Haojin Tang <[email protected]> |
Backend: intExuBlock may also need `frm` (like i2f)
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16782ac3 |
| 06-Oct-2023 |
Haojin Tang <[email protected]> |
Backend: DontCare `ctrlBlock.perfinfo` temporarily
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fa3c7ee7 |
| 06-Oct-2023 |
Haojin Tang <[email protected]> |
Backend: fix connection order of fenceio
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7eea175b |
| 06-Oct-2023 |
Haojin Tang <[email protected]> |
Backend: connect hardId to dataPath
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e6adfa60 |
| 06-Oct-2023 |
Haojin Tang <[email protected]> |
XSCore: connect `fenceToSbuffer` directly to fenceio
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86e04cc0 |
| 06-Oct-2023 |
Haojin Tang <[email protected]> |
Backend: fix connection order of `csrio.perf`
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| #
9b8ed6d6 |
| 06-Oct-2023 |
Haojin Tang <[email protected]> |
Backend: remove unused `ftqIdx` and `ftqOffset` from ExuOutput
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| #
36a293c0 |
| 06-Oct-2023 |
Haojin Tang <[email protected]> |
cpuHalted: wire it to false.B and mark it with TODO
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06083203 |
| 06-Oct-2023 |
Haojin Tang <[email protected]> |
MemCommon: only use robIdx and sqIdx in MemWaitUpdateReq
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8044e48c |
| 06-Oct-2023 |
Haojin Tang <[email protected]> |
Backend: read loadPc for MemBlock
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b7d9e8d5 |
| 28-Sep-2023 |
xiaofeibao-xjtu <[email protected]> |
backend: parameterized generation debug IO and difftest IO
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| #
96e858ba |
| 24-Sep-2023 |
Xuan Hu <[email protected]> |
backend: add perfDebugInfo
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| #
d8a24b06 |
| 20-Sep-2023 |
zhanglyGit <[email protected]> |
Backend: refactor jump targetMem in CtrlBlock
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| #
bc7d6943 |
| 08-Sep-2023 |
zhanglyGit <[email protected]> |
Backend: implement speculative busytable supporting fastWakeUp and cancel
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