Backend,Frontend: pass flag of FtqPtr to TargetMem to avoid read out-of-date predict target (#3184)

* Hold newest predict target everytime it is updated by frontend.
* Don't use out-of-date predict

Backend,Frontend: pass flag of FtqPtr to TargetMem to avoid read out-of-date predict target (#3184)

* Hold newest predict target everytime it is updated by frontend.
* Don't use out-of-date predict value even if FtqIdx match.

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bpu: gate reset_vector (#2790)

ICache: implement new ICache (#3051)

Co-authored-by: xu_zh <[email protected]>

L1CacheErrorInfo: code refactor for correct and convenient clockgate (#3044)

frontend: add a gpaddr write data path

add a data path in Ifu, which write gpaddr to backend at the same time
as write to IBuffer

Merge remote-tracking branch 'upstream/master' into tmp-master

TODO: add gpaddr data path from frontend to backend

RVH: rewrite the logic of getting gpaddr when guest page fault

Configs: correct MaxHartIdBits (#2838)

Currently, many different lengths of HartId in Xiangshan, making it hard to
configure it to scale more than 16 cores since we have set 4bits somewhere.
This

Configs: correct MaxHartIdBits (#2838)

Currently, many different lengths of HartId in Xiangshan, making it hard to
configure it to scale more than 16 cores since we have set 4bits somewhere.
This commit corrects MaxHartIdBits in config and uses MaxHartIDBits where
it needs to get this solved.

Signed-off-by: Yangyu Chen <[email protected]>

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Decode,IBuffer: fix circle dependency deadlock

* Add a new field `canAccept` passed from decode to notice `IBuffer` that it can deq new instructions.
* IBuffer.io.out(i).ready depends on IBuffer.io.

Decode,IBuffer: fix circle dependency deadlock

* Add a new field `canAccept` passed from decode to notice `IBuffer` that it can deq new instructions.
* IBuffer.io.out(i).ready depends on IBuffer.io.out(i).ready.
* Since decode promises accepting insts in order, priority encoder is used to simplify the accumulation of `numDeq`.
* `numDeq` records the number of deq insts from ibuffer, not from bypass. And it is used to update deqPtr and corresponding deqBankPtr.
* Guard numFromFetch calculation with io.in.valid to avoid updating enqPtr when input signal is invalid.
* Todo: check ibuffer timing, critical path maybe ibuffer.io.out.valid -> ibuffer.io.out.ready -> ibuffer.validEntries -> nextValidEntries -> allowEnq

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Merge remote-tracking branch 'upstream/master' into backendq

Debug Module: cherry-pick debug module from nanhu

Rebase Timing Fix of Memblock from fix-timing branch (#2501)

* fix LQ timing

* l1pf: fix pf queue to ldu timing

* disable ecc path for timing analysis

* TODO: remove this

* fix pipeline

Rebase Timing Fix of Memblock from fix-timing branch (#2501)

* fix LQ timing

* l1pf: fix pf queue to ldu timing

* disable ecc path for timing analysis

* TODO: remove this

* fix pipeline

* memblock: add a Reg between inner/outer reset_vec

* missqueue: make mem_grant always ready

* Enable ECC path again

* remove fast replay reorder logic

* l1pf: use chosen of arbiter to improve timing

* remove reorder remain logic

* mq: use ParallelORR instead of orR

* Strengthen the conditions for load to load path for timing

* fix load to load data select for timing

* refactoring lq replay valid logic

* fix replay port

* fix load unit s0 arbitor logic

* add topdown wiring

* fix ldu ecc path

* remove lateKill

* ecc: physically remove ecc in DataArray

* loadpipe: use ParallelORR and ParallelMux for timing

* mainpipe: use ParallelMux and ParallelorR for timing

* fix fast replay is killed at s1

* fix replay cancel logic

* fix mq nack feedback logic

* sms: fix pf queue tlb req logic for timing

* kill load at s1

* fix loadqueuereplay enq logic

* opt raw rollback arbiter logic

* fix ecc_delayed writeback logic

* train all l1 pf and sms at load s3 for better timing

* disable load to load forward

* Revert "kill load at s1"

This reverts commit 56d47582ad4dd9c83373fb2db2a0709075485d4d.

* fix s0 kill logic

* ITLBRepeater: Add one more buffer when PTW resp

* remove trigger

* fix feedback_slow logic

* add latch in uncachebuffer rollback

* remove trigger in port

* fast replay: use dcache ready

* fix replay logic at s1

* uncache: fix uncache writeback

* fix delay kill logic

* fix clean exception loigc at s3

* fix ldu rollback logic

* fix ldu rollback valid logic

---------

Co-authored-by: sfencevma <[email protected]>
Co-authored-by: XiChen <[email protected]>
Co-authored-by: Lyn <[email protected]>
Co-authored-by: good-circle <[email protected]>

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Merge timing fixes of XSTile into Master (#2488)

* Timing: add buffer in Frontend-L2 path
double buffer applied in icache-L2 (both at MemBlock)
single buffer applied in frontend-MMIO (at MemBlock)

Merge timing fixes of XSTile into Master (#2488)

* Timing: add buffer in Frontend-L2 path
double buffer applied in icache-L2 (both at MemBlock)
single buffer applied in frontend-MMIO (at MemBlock)

* Move l1d-to-l2 buffer from L2Top to MemBlock to balance timing

* Use arcane methods to keep Frontend MMIO port name for MemBlock

* Add Reg for L2-L1 Hint in both L2Top and MemBlock

* Add Buffer between l1_xbar and L2

* Add buffer for beu_error in MemBlock

* Frontend: add buffer for reset_vector in Frontend-memBlock path (by ssszwic)

* Move one buffer in L1-L2 from MemBlock to L2Top

* Add another buffer in frontend MMIO path

* Fix compilation error

* Hint revert to master design, the Reg here is canceled because we have this reg in L2

* Add a third buffer in I-MMIO path

* Add a third buffer in PTW-L2 path at L2Top(above xbar)

* Fix I-mmio buffer constant values wrongly assigned

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hpm: fix selection logic and typo (#1618) (#2483)

Co-authored-by: Chen Xi <[email protected]>

refactor: use banked IBuffer (#2441)

* ibuffer: refactor to raw Vec

- use banked register to reduce read port logic

ibuffer: fix assertion error

ibuffer: fix various typo assertion bug

i

refactor: use banked IBuffer (#2441)

* ibuffer: refactor to raw Vec

- use banked register to reduce read port logic

ibuffer: fix assertion error

ibuffer: fix various typo assertion bug

ibuffer: fix entry write mux

ibuffer: fix deqPtr movement

ibuffer: fix NBank larger than DecodeWidth

ibuffer: add comments about new design

config: change MinimalConfig IBufNBank back to 2

config: use DecodeWidth as IBufNBank

config: remove IBufNBank from XSCoreParameters

Revert "config: remove IBufNBank from XSCoreParameters"

This reverts commit 4da836590cc3af168e1cf2582269fc15394b514e.

Revert "config: use DecodeWidth as IBufNBank"

This reverts commit d04bddb551f846ad65db2a2cc903d26251be0ee8.

* ibuffer: use Mux1H to rewrite read port

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Frontend: delete unnecessary dontTouch in frontend (#2414)

Bump rocket-chip (#2353)

TLB: Pass hartId through IO (#2342)

LazyModule: do not inline lazy modules in XS (#2311)

top-down: do not use boring utils (#2304)

TLB: Modify TLB structure to full-asso with 48 entries (#2289)

* TLB: Modify TLB structure to full-asso with 48 entries

* TLB: Fix wrong changes on XSDts

* TLB: modify signal naming

Frontend: timing optimization (#2291)

Predecode delayed to f3 and use partial paralle valid generation logic
Remove CacheOp support in ICache

icache: change itlb port to no-blocked and new fdip (#2277)

Frontend: add basic instruction stream check (#2265)

PTW: Move PTW to MemBlock (#2211)

* PTW: Move PTW to MemBlock

Move itlbrepeater to Frontend and MemBlock, dtlbrepeater to MemBlock,
L2 TLB (PTW) and ptw_to_l2_buffer to Memblock for better parti

PTW: Move PTW to MemBlock (#2211)

* PTW: Move PTW to MemBlock

Move itlbrepeater to Frontend and MemBlock, dtlbrepeater to MemBlock,
L2 TLB (PTW) and ptw_to_l2_buffer to Memblock for better partition.

* MMU: Fix sfence delay to synchronize modules

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