| #
bcbd7e28 |
| 09-Oct-2019 |
Zihao Yu <[email protected]> |
noop,icache: connect instruction mmio
|
| #
9a5b5207 |
| 03-Oct-2019 |
Zihao Yu <[email protected]> |
test,SimMMIO: remove DeviceHelper
|
| #
fe820c3d |
| 01-Oct-2019 |
Zihao Yu <[email protected]> |
noop,fu,CSR: add mie and mip for machine timer interrupt
TODO:
* Injecting interrupts in decode stage with NOP.
* Save mstatus.mie to mstatus.mpie
|
| #
891d22aa |
| 01-Oct-2019 |
Zihao Yu <[email protected]> |
device,AXI4Timer: support mtime and mtimecmp
|
| #
43002b01 |
| 30-Sep-2019 |
Zihao Yu <[email protected]> |
device,AXI4VGA: add FBHelper for emu
|
| #
11348640 |
| 30-Sep-2019 |
Zihao Yu <[email protected]> |
device,AXI4VGA: change fb to AXI4Lite, and connect vga at SimMMIO
|
| #
d7763dc0 |
| 26-Sep-2019 |
Zihao Yu <[email protected]> |
device: add AXI4UART
* only support write
|
| #
9c43f7c7 |
| 26-Sep-2019 |
Zihao Yu <[email protected]> |
test,SimMMIO: use crossbar to connect timer
|
| #
f9f9abc5 |
| 18-Sep-2019 |
Zihao Yu <[email protected]> |
Merge branch 'master' into dev-rv64
|
| #
aa38aa4d |
| 11-Sep-2019 |
William Wang <[email protected]> |
fix(cache): fix some problems in 64bit cache, dummy test passed
|
| #
ad255e6c |
| 07-Sep-2019 |
Zihao Yu <[email protected]> |
bus,SimpleBus: unify SimpleBusUL and SimpleBusUH
|
| #
8f36f779 |
| 01-Sep-2019 |
Zihao Yu <[email protected]> |
bus,simplebus: divide into SimpleBusUL and SimpleBusUH
* SimpleBusUL is used for MMIO and SimpleBusUH is used for memory
* should refactor SimpleBus2AXI4Converter to support SimpleBusUL and
Simple
bus,simplebus: divide into SimpleBusUL and SimpleBusUH
* SimpleBusUL is used for MMIO and SimpleBusUH is used for memory
* should refactor SimpleBus2AXI4Converter to support SimpleBusUL and
SimpleBusUH
show more ...
|
| #
39be9e08 |
| 01-Sep-2019 |
Zihao Yu <[email protected]> |
bus,simplebus: add burst signals
|
| #
98a49f6a |
| 31-Aug-2019 |
Zihao Yu <[email protected]> |
bus,simplebus: directly use UInt() for user signal
* chisel 3.2 supports userBits == 0
|
| #
b47399fb |
| 23-Aug-2019 |
Zihao Yu <[email protected]> |
update to chisel3.2
|
| #
4abbb32b |
| 27-May-2019 |
Zihao Yu <[email protected]> |
test,device: fix reset bug
|
| #
3d1cbb5b |
| 10-May-2019 |
Zihao Yu <[email protected]> |
clean up
|
| #
13cfb810 |
| 10-May-2019 |
Zihao Yu <[email protected]> |
implement keyboard and vga in emu
|
| #
af5eab61 |
| 10-May-2019 |
Zihao Yu <[email protected]> |
move basic device handling to verilator by DPI
* TODO: implement keyboard and vga
|
| #
2b40c882 |
| 01-Mar-2019 |
Zihao Yu <[email protected]> |
test,top,SimMMIO: modify device address to match FPGA
|
| #
6824092d |
| 26-Feb-2019 |
Zihao Yu <[email protected]> |
bus,simplebus,Crossbar: fix in.out.req.valid assignment
|
| #
36ac49e5 |
| 26-Feb-2019 |
Zihao Yu <[email protected]> |
bus,simplebus: add basic crossbar
|
| #
d373554f |
| 25-Feb-2019 |
Zihao Yu <[email protected]> |
bus,simplebus: refactor a/w/r into req/resp
|
| #
5293565b |
| 25-Feb-2019 |
Zihao Yu <[email protected]> |
bus: re-organize the directory structure
|
| #
11f11fdf |
| 25-Feb-2019 |
Zihao Yu <[email protected]> |
memory: rename MemIO to SimpleBus
|