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Searched defs:s1_req (Results 1 – 7 of 7) sorted by relevance

/XiangShan/src/main/scala/xiangshan/mem/lsqueue/
H A DLoadExceptionBuffer.scala49 val s1_req = VecInit(io.req.map(_.bits)) constant
H A DLoadQueueUncache.scala350 val s1_req = VecInit(s1_sortedVec.map(_.bits)) constant
H A DStoreMisalignBuffer.scala144 val s1_req = VecInit(io.enq.map(_.req.bits)) constant
H A DStoreQueue.scala91 val s1_req = VecInit(io.storeAddrIn.map(_.bits)) constant
/XiangShan/src/main/scala/xiangshan/cache/dcache/storepipe/
H A DStorePipe.scala116 val s1_req = RegEnable(s0_req, s0_fire) constant
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/
H A DLoadPipe.scala176 val s1_req = RegEnable(s0_req, s0_fire) constant
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/
H A DMainPipe.scala299 val s1_req = RegEnable(s0_req, s0_fire) constant