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/linux-6.14.4/arch/arm64/kvm/hyp/
Dexception.c75 * This performs the exception entry at a given EL (@target_mode), stashing PC
77 * The EL passed to this function *must* be a non-secure, privileged mode with
85 * For the SPSR_ELx layout for AArch64, see ARM DDI 0487E.a page C5-429.
86 * For the SPSR_ELx layout for AArch32, see ARM DDI 0487E.a page C5-426.
140 // See ARM DDI 0487E.a, page D5-2579. in enter_exception64()
144 // See ARM DDI 0487E.a, page D5-2578. in enter_exception64()
150 // See ARM DDI 0487E.a, page D2-2452. in enter_exception64()
153 // See ARM DDI 0487E.a, page D1-2306. in enter_exception64()
156 // See ARM DDI 0487E.a, page D13-3258 in enter_exception64()
161 // See ARM DDI 0487E.a, pages D1-2293 to D1-2294. in enter_exception64()
[all …]
/linux-6.14.4/Documentation/trace/coresight/
Dcoresight-cpu-debug.rst11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
12 (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
43 - The driver supports a CPU running in either AArch64 or AArch32 mode. The
44 registers naming convention is a bit different between them, AArch64 uses
45 'ED' for register prefix (ARM DDI 0487A.k, chapter H9.1) and AArch32 uses
46 'DBG' as prefix (ARM DDI 0487A.k, chapter G5.1). The driver is unified to
49 - ARMv8-a (ARM DDI 0487A.k) and ARMv7-a (ARM DDI 0406C.b) have different
52 If PCSROffset=0b0000, on ARMv8-a the feature of EDPCSR is not implemented;
53 but ARMv7-a defines "PCSR samples are offset by a value that depends on the
54 instruction set state". For ARMv7-a, the driver checks furthermore if CPU
[all …]
/linux-6.14.4/tools/testing/selftests/arm64/signal/
Dsve_helpers.c37 * terminating, bail out here when we find a higher VL than in sve_fill_vls()
39 * See the ARM ARM, DDI 0487K.a, B1.4.2: I_QQRNR and I_NWYBP. in sve_fill_vls()
/linux-6.14.4/Documentation/arch/arm64/
Dhugetlbpage.rst18 These are regular hugepages where a pmd or a pud page table entry points to a
26 The architecture provides a contiguous bit in the translation table entries
27 (D4.5.3, ARM DDI 0487C.a) that hints to the MMU to indicate that it is one of a
28 contiguous set of entries that can be cached in a single TLB entry.
Dmops.rst7 A MOPS memory copy/set operation consists of three consecutive CPY* or SET*
8 instructions: a prologue, main and epilogue (for example: CPYP, CPYM, CPYE).
10 A main or epilogue instruction can take a MOPS exception for various reasons,
11 for example when a task is migrated to a CPU with a different MOPS
18 the Arm Architecture Reference Manual DDI 0487K.a (Arm ARM).
25 A hypervisor running a Linux guest must handle all MOPS exceptions from the
27 For example, a MOPS exception can be taken when the hypervisor migrates a vCPU
28 to another physical CPU with a different MOPS implementation.
37 - Set the guest's PSTATE.SS to 0 in the exception handler, to handle a
40 Note: Clearing PSTATE.SS is needed so that a single step exception is taken
/linux-6.14.4/Documentation/translations/zh_CN/arch/arm64/
Dhugetlbpage.rst29 架构中转换页表条目(D4.5.3, ARM DDI 0487C.a)中提供一个连续
Dbooting.txt4 original document maintainer directly. However, if you have a problem
7 or if there is a problem with the translation.
175 ARM DDI 0487A
233 ARM DEN 0022A：用于 ARM 上的电源状态协调接口系统软件）中描述的
236 *译者注: ARM DEN 0022A 已更新到 ARM DEN 0022C。
/linux-6.14.4/Documentation/translations/zh_TW/arch/arm64/
Dhugetlbpage.rst32 架構中轉換頁表條目(D4.5.3, ARM DDI 0487C.a)中提供一個連續
Dbooting.txt6 original document maintainer directly. However, if you have a problem
9 or if there is a problem with the translation.
179 ARM DDI 0487A
237 ARM DEN 0022A：用於 ARM 上的電源狀態協調接口系統軟件）中描述的
240 *譯者注: ARM DEN 0022A 已更新到 ARM DEN 0022C。
/linux-6.14.4/Documentation/devicetree/bindings/arm/
Darm,coresight-cpu-debug.yaml17 reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
53 A phandle to the cpu this debug component is bound to.
59 A phandle to the debug power domain if the debug logic has its own
/linux-6.14.4/arch/arm64/kernel/
Dcpuinfo.c234 * Dump out the common processor features in a single line. in c_show()
236 * rather than attempting to parse this, but there's a body of in c_show()
305 * The ARM ARM uses the phrase "32-bit register" to describe a register
306 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however
308 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI
309 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit.
464 * when there is a mismatch across the CPUs. Keep track of the in __cpuinfo_store_cpu()
Dmte.c127 * Note: If in future KASAN acquires a runtime switching in mte_enable_kernel_async()
145 * Note: If in future KASAN acquires a runtime switching in mte_enable_kernel_asymm()
171 * (per ARM DDI 0487F.c table D13-1). in mte_check_tfsr_el1()
290 * lead to the wrong memory type being used for a brief window during in mte_cpu_setup()
293 * CnP is not a boot feature so MTE gets enabled before CnP, but let's in mte_cpu_setup()
366 * Userspace could see a mix of both sync and async anyway due in set_mte_ctrl()
615 * A read is sufficient for mte, the caller should have probed in mte_probe_user_range()
/linux-6.14.4/arch/arm64/include/asm/
Dkgdb.h43 * To expand a little on the "most versions of it"... when the gdb remote
44 * protocol for AArch64 was developed it depended on a statement in the
45 * Architecture Reference Manual that claimed "SPSR_ELx is a 32-bit register".
46 * and, as a result, allocated only 32-bits for the PSTATE in the remote
47 * protocol. In fact this statement is still present in ARM DDI 0487A.i.
49 * Unfortunately "is a 32-bit register" has a very special meaning for
51 * RES0.". RES0 is heavily used in the ARM architecture documents as a
52 * way to leave space for future architecture changes. So to translate a
54 * manuals, what "is a 32-bit register" actually means in this context is
55 * "is a 64-bit register but one with no meaning allocated to any of the
[all …]
Ddaifflags.h34 /* Don't really care for a dsb here, we don't intend to enable IRQs */ in local_daif_mask()
98 * From the ARM ARM DDI 0487D.a, section D1.7.1 in local_daif_restore()
109 * interrupts with a lower priority than PMR is signaled in local_daif_restore()
Dcache.h93 * According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
Dtraps.h54 * to indicate whether this ESR has a RAS encoding. CPUs without this feature
55 * have a ISS-Valid bit in the same position.
56 * If this bit is set, we know its not a RAS SError.
58 * errors share the same encoding as an all-zeros encoding from a CPU that
75 * Return the AET bits from a RAS SError's ESR.
86 /* Not a RAS error, we can't interpret the ESR. */ in arm64_ras_serror_get_severity()
118 * Put the registers back in the original format suitable for a in arm64_mops_reset_regs()
120 * Arm ARM (DDI 0487I.a) rules CNTMJ and MWFQH. in arm64_mops_reset_regs()
125 /* Format is from Option A; forward set */ in arm64_mops_reset_regs()
140 /* Format is from Option A */ in arm64_mops_reset_regs()
Dkvm_arm.h89 * AMO: Override CPSR.A and enable signaling with VA
93 * PTW: Take a stage2 fault if a stage1 walk steps in device memory
152 * 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are
168 * See D.10.2.121, VTCR_EL2, in ARM DDI 0487C.a
186 * Where TGRAN_SL0_BASE is a magic number depending on the page size:
223 * descriptors in section D4.2.8 in ARM DDI 0487C.a.
228 * algorithm determines the alignment of a table base address at a given
232 * depending on the T0SZ, the value of "x" is defined based on a
233 * Magic constant for a given PAGE_SIZE and Entry Level. The
255 * We have a magic formula for the Magic_N below:
[all …]
Dcpufeature.h32 * The safe value of a CPUID feature field is dependent on the implications
39 * a field when EXACT is specified, failing which, the safe value specified
44 FTR_EXACT, /* Use a predefined safe value */
80 * A @mask field set to full-1 indicates that the corresponding field
81 * in @val is a valid override.
83 * A @mask field set to full-0 with the corresponding @val field set
86 * A @mask field set to full-0 with the corresponding @val field set
125 * 1) Scope of Detection : The system detects a given capability by
127 * value of a field in CPU ID feature register or checking the cpu
128 * model. The capability provides a call back ( @matches() ) to
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Dkvm_emulate.h154 * vcpu_get_reg and vcpu_set_reg should always be passed a register number
155 * coming from a read of ESR_EL2. Otherwise, it may give the wrong result on
212 * We are in a hypervisor context if the vcpu mode is EL2 or in is_hyp_ctxt()
217 * rest of the KVM code, and will result in a misbehaving guest. in is_hyp_ctxt()
232 * In ARM DDI 0487E.a see:
424 * Only a permission fault on a S1PTW should be in kvm_is_write_fault()
425 * considered as a write. Otherwise, page tables baked in kvm_is_write_fault()
426 * in a read-only memslot will result in an exception in kvm_is_write_fault()
430 * guest is using any of HW AF/DB: a translation fault in kvm_is_write_fault()
432 * first), then a permission fault to allow the flags in kvm_is_write_fault()
[all …]
Dtlbflush.h28 * on whether a particular TLBI operation takes an argument or
57 /* This macro creates a properly formatted VA operand for the TLBI */
98 * a non-hinted invalidation. Any provided level outside the hint range
128 * This macro creates a properly formatted VA operand for the TLB RANGE. The
141 * 0487J.a section C5.5.60 "TLBI VAE1IS, TLBI VAE1ISNXS, TLB Invalidate by VA,
173 * significant for a maximum of MAX_TLBI_RANGE_PAGES pages. If
219 * kernel mappings rather than a particular user address space.
224 * Invalidate a single user mapping for address 'addr' in the
226 * operation only invalidates a single, last-level page-table
237 * Invalidate a single kernel mapping for address 'addr' on all
[all …]
Dassembler.h30 * Provide a wxN alias for each wN register so what we can paste a xN
31 * reference after a 'w' to obtain the 32-bit version.
58 isb // Take effect before a subsequent clear of DAIF.D
150 * Define a macro that constructs a 64-bit value by concatenating two
178 * @tmp: optional 64-bit scratch register to be used if <dst> is a
365 * Macro to perform a data cache maintenance for the interval
406 * Macro to perform a data cache maintenance for the interval
445 * load_ttbr1 - install @pgtbl as a TTBR1 page table
458 * in the tlb, switch the ttbr to a zero page when we invalidate the old
459 * records. D4.7.1 'General TLB maintenance requirements' in ARM DDI 0487A.i
[all …]
/linux-6.14.4/drivers/acpi/arm64/
Dgtdt.c127 * Return: true if the timer HW state is lost when a CPU enters an idle state,
154 * @platform_timer_count: It points to a integer variable which is used
227 * See ARM DDI 0487A.k_iss10775, page I1-5129, Table I1-3 in gtdt_parse_timer_block()
277 * See ARM DDI 0487A.k_iss10775, page I1-5130, Table I1-4 in gtdt_parse_timer_block()
311 * @timer_count: It points to a integer variable which is used for storing the
341 * Initialize a SBSA generic Watchdog platform device info from GTDT
360 pr_debug("found a Watchdog (0x%llx/0x%llx gsi:%u flags:0x%x).\n", in gtdt_import_sbsa_gwdt()
377 * Add a platform device named "sbsa-gwdt" to match the platform driver. in gtdt_import_sbsa_gwdt()
/linux-6.14.4/drivers/hwtracing/coresight/
Dcoresight-cpu-debug.c125 * According to ARM DDI 0487A.k, before access external debug
218 * As described in ARM DDI 0487A.k, if the processing in debug_read_regs()
228 * A read of the EDPCSR normally has the side-effect of in debug_read_regs()
359 * In ARM DDI 0487A.k, the EDDEVID1.PCSROffset is used to in debug_init_arch_data()
/linux-6.14.4/arch/arm64/mm/
Dhugetlbpage.c146 * Changing some bits of contiguous entries requires us to follow a
148 * before we can change any entries. See ARM DDI 0487A.k_iss10775,
192 * Changing some bits of contiguous entries requires us to follow a
194 * before we can change any entries. See ARM DDI 0487A.k_iss10775,
405 * For a contiguous huge pte range we need to check whether or not write
407 * all the contiguous ptes we need to check whether or not there is a
511 * levels (PUD, CONT PMD, PMD, CONT PTE) for a given base in hugetlbpage_init()
/linux-6.14.4/tools/arch/arm64/include/asm/
Dsysreg.h21 * C5.2, version:ARM DDI 0487A.f)
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
84 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions
956 * KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it
1141 * The "Z" constraint normally means a zero immediate, but when combined with
1172 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the

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