| #
c90e3eac |
| 26-Jan-2024 |
Ziyue Zhang <[email protected]> |
rv64v: fix uop spilt and mask generate for vlm
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| #
712a039e |
| 18-Jan-2024 |
xiaofeibao-xjtu <[email protected]> |
backend: og1 src select timing optimize
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| #
ff3fcdf1 |
| 15-Dec-2023 |
xiaofeibao-xjtu <[email protected]> |
Dispatch: split int dispatch to two regions
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| #
145dfe39 |
| 17-Feb-2024 |
Xuan Hu <[email protected]> |
Backend: optimize resp signal
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| #
f08a822f |
| 27-Dec-2023 |
zhanglyGit <[email protected]> |
Backend: optimize resp signal
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| #
596af5d2 |
| 20-Dec-2023 |
Haojin Tang <[email protected]> |
Scheduler: implement wakeup from LoadUnit
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| #
aa2bcc31 |
| 19-Dec-2023 |
zhanglyGit <[email protected]> |
Backend: refactor Entries
|
| #
5f80df32 |
| 15-Dec-2023 |
xiaofeibao-xjtu <[email protected]> |
IQ: remove unused pc and ftqptr
|
| #
4c5a0d77 |
| 06-Dec-2023 |
xiaofeibao-xjtu <[email protected]> |
WakeupQueue: Copy all bits
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| #
0c7ebb58 |
| 04-Dec-2023 |
xiaofeibao-xjtu <[email protected]> |
WakeupQueue: pdest copy
|
| #
1f35da39 |
| 29-Nov-2023 |
xiaofeibao-xjtu <[email protected]> |
backend: change vfSchdParams, add PipelineConnect name
|
| #
9910ea36 |
| 17-Nov-2023 |
zhanglyGit <[email protected]> |
Backend: refactor load finalBlock timing
|
| #
4fa00a44 |
| 17-Nov-2023 |
zhanglyGit <[email protected]> |
Backend: refactor load finalBlock timing
|
| #
fb445e8d |
| 16-Nov-2023 |
zhanglyGit <[email protected]> |
Backend: remove cancelNetwork and some cancel false path
|
| #
cda1c534 |
| 24-Oct-2023 |
xiaofeibao-xjtu <[email protected]> |
Rob: optimize timing, remove vconfig debugIO
|
| #
8d081717 |
| 24-Oct-2023 |
szw_kaixin <[email protected]> |
backend: control dontTouch opcode by debugEn
|
| #
1548ca99 |
| 14-Dec-2023 |
Haojin Tang <[email protected]> |
mdp: enable LFST by default
|
| #
59a1db8a |
| 14-Dec-2023 |
Haojin Tang <[email protected]> |
mdp: connect missing wires
|
| #
e77d3114 |
| 14-Dec-2023 |
Haojin Tang <[email protected]> |
Issue: split LDU0 from STA0
|
| #
272ec6b1 |
| 14-Dec-2023 |
Haojin Tang <[email protected]> |
stIn: connect missing wire
|
| #
d97a1af7 |
| 08-Jan-2024 |
Xuan Hu <[email protected]> |
Backend,MemBlock,params: expand the width of enq of LSQ
|
| #
31c51290 |
| 28-Dec-2023 |
zhanglinjuan <[email protected]> |
Fix bugs in exceptional stores (#2600)
* VPPU: fix timing mismatch between isMvnr and data
* STU,HYU,VSFlowQueue: add exceptionVec in store pipeline feedbacks
* VSFlowQueue: add exception buff
Fix bugs in exceptional stores (#2600)
* VPPU: fix timing mismatch between isMvnr and data
* STU,HYU,VSFlowQueue: add exceptionVec in store pipeline feedbacks
* VSFlowQueue: add exception buffer to record exceptional vaddr
* MemBlock: modify signal naming
show more ...
|
| #
9d8d7860 |
| 03-Jan-2024 |
Xuan Hu <[email protected]> |
Backend: add predecode info in load pipeline
|
| #
ec86549e |
| 02-Jan-2024 |
sfencevma <[email protected]> |
MemBlock: enable 3ld3st (#2524)
* enable 3ld3st
* assign enqLsq
* fix IssQueSize
* remove performance regression
* MMU: Fix ptwrepeater when 3ld + 3st
* fix minimal config params
*
MemBlock: enable 3ld3st (#2524)
* enable 3ld3st
* assign enqLsq
* fix IssQueSize
* remove performance regression
* MMU: Fix ptwrepeater when 3ld + 3st
* fix minimal config params
* fix minimal config LoadQueueReplaySize
* add 3ld3st switch
* fix bank conflict valid logic
* fix strict memory ambiguous logic
* fix wakeup logic
* disable 3ld3st by default
* modify minimal config params
---------
Co-authored-by: Lyn <[email protected]>
Co-authored-by: good-circle <[email protected]>
show more ...
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| #
4c7680e0 |
| 08-Dec-2023 |
Xuan Hu <[email protected]> |
Backend: add VTypeBuffer to deduce size of rob
|