predecode - OpenGrok history log for /XiangShan/src/main/scala/xiangshan/backend/decode/isa/predecode

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
b8b991d6	20-Jul-2023	Guokai Chen <[email protected]>	Predecode: fix ebreak predecoded as jalr (#2186) /XiangShan/.github/ISSUE_TEMPLATE/bug_report.md /XiangShan/.github/ISSUE_TEMPLATE/feature_request.md /XiangShan/.github/workflows/check_verilog.py /XiangShan/.github/workflows/emu.yml /XiangShan/.github/workflows/nightly.yml /XiangShan/.gitignore /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/Makefile.test /XiangShan/README.md /XiangShan/build.sc /XiangShan/coupledL2 /XiangShan/debug/Makefile /XiangShan/debug/local_ci.py /XiangShan/difftest /XiangShan/fudian /XiangShan/huancun /XiangShan/images/wechat.png /XiangShan/images/xs-arch-nanhu.svg /XiangShan/images/xs-arch-yanqihu.svg /XiangShan/readme.zh-cn.md /XiangShan/ready-to-run /XiangShan/rocket-chip /XiangShan/scripts/constantHelper.py /XiangShan/scripts/gen_sep_mem.sh /XiangShan/scripts/top-down/.gitignore /XiangShan/scripts/top-down/README.md /XiangShan/scripts/top-down/file.f /XiangShan/scripts/top-down/json2f.py /XiangShan/scripts/top-down/run_emu.sh /XiangShan/scripts/top-down/top-down.sh /XiangShan/scripts/top-down/top_down.py /XiangShan/scripts/top-down/xsrun /XiangShan/scripts/utils/convert.sh /XiangShan/scripts/utils/convert_dir.sh /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/device/AXI4IntrGenerator.scala /XiangShan/src/main/scala/device/AXI4Keyboard.scala /XiangShan/src/main/scala/device/AXI4Memory.scala /XiangShan/src/main/scala/device/AXI4Plic.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4SlaveModule.scala /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/AXI4VGA.scala /XiangShan/src/main/scala/device/RocketDebugWrapper.scala /XiangShan/src/main/scala/device/TLPMA/TLPMA.scala /XiangShan/src/main/scala/gpu/GPU.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/BusPerfMonitor.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Generator.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/ArbiterHelper.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/OverrideableQueue.scala /XiangShan/src/main/scala/utils/PerfCounterUtils.scala /XiangShan/src/main/scala/utils/Trigger.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/DbEntry.scala /XiangShan/src/main/scala/xiangshan/PMParameters.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSDts.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FUBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala predecode.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Rs.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/IndexMapping.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Bku.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/InputBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CryptoUtils.scala /XiangShan/src/main/scala/xiangshan/backend/issue/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/PayloadArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SelectPolicy.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/WakeupQueue.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/CacheConstants.scala /XiangShan/src/main/scala/xiangshan/cache/CacheInstruction.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWPU.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/FakeDCache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AMOALU.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/RefillPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/AsynchronousMetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLBMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TlbPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/Prefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/StreamPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Composer.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBankedArray.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala /XiangShan/src/main/scala/xiangshan/mem/MaskedDataModule.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/MemTrace.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/FreeList.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/WaitTable.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchInterface.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/DatamoduleResultBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/DummyVLSQ.scala /XiangShan/src/main/scala/xiangshan/mem/vector/MemVectorInterface.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xstransforms/PrintControl.scala /XiangShan/src/main/scala/xstransforms/PrintModuleName.scala /XiangShan/src/test/scala/fu/IntDiv.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/src/test/scala/xiangshan/DecodeTest.scala /XiangShan/src/test/scala/xiangshan/XSTester.scala /XiangShan/utility
d57bda64	18-Aug-2021	JinYue <[email protected]>	Merge branch 'decoupled-frontend-ifu' into decoupled-frontend /XiangShan/.github/workflows/emu.yml /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/build.sc /XiangShan/debug/Makefile /XiangShan/difftest /XiangShan/ready-to-run /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/utils/DataModuleTemplate.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/PMA.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FUBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala predecode.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wb.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/ICache.scala /XiangShan/src/main/scala/xiangshan/cache/ICacheMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/InstrUncache.scala /XiangShan/src/main/scala/xiangshan/cache/L1plusCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/L1plusPrefetcher.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/Composer.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/ICache.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/SC.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/local.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/SimTop.scala
35ee668d	16-Aug-2021	JinYue <[email protected]>	PreDecode: add exception logic * set instruction to NOP when exception /XiangShan/.gitignore /XiangShan/.gitmodules /XiangShan/.mill-version /XiangShan/Makefile /XiangShan/README.md /XiangShan/build.sbt /XiangShan/build.sc /XiangShan/readme.zh-cn.md /XiangShan/ready-to-run /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/DataModuleTemplate.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/PMA.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FloatBlock.scala /XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala predecode.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/PayloadArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SelectPolicy.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/ICache.scala /XiangShan/src/main/scala/xiangshan/cache/ICacheMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/InstrUncache.scala /XiangShan/src/main/scala/xiangshan/cache/L1plusCache.scala /XiangShan/src/main/scala/xiangshan/cache/PTW.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/L1plusPrefetcher.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/Composer.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/Ftq.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/ICache.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/local.scala /XiangShan/src/main/scala/xiangshan/decoupled-frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xstransforms/PrintControl.scala /XiangShan/src/test/csrc/common/common.h /XiangShan/src/test/csrc/difftest/difftest.cpp /XiangShan/src/test/csrc/difftest/difftest.h /XiangShan/src/test/csrc/difftest/goldenmem.cpp /XiangShan/src/test/csrc/difftest/nemuproxy.cpp /XiangShan/src/test/csrc/vcs/main.cpp /XiangShan/src/test/csrc/verilator/emu.cpp /XiangShan/src/test/csrc/verilator/emu.h /XiangShan/src/test/csrc/verilator/main.cpp /XiangShan/src/test/vsrc/vcs/top.v /XiangShan/verilator.mk /XiangShan/xs-arch-simple.svg
f320e0f0	24-Jul-2021	Yinan Xu <[email protected]>	misc: update PCL information (#899) XiangShan is jointly released by ICT and PCL. /XiangShan/.gitignore /XiangShan/.gitmodules /XiangShan/.mill-version /XiangShan/Makefile /XiangShan/README.md /XiangShan/build.sbt /XiangShan/build.sc /XiangShan/debug/Makefile /XiangShan/debug/cputest.sh /XiangShan/debug/env.sh /XiangShan/debug/perf_sbuffer.sh /XiangShan/debug/sc_stat.sh /XiangShan/readme.zh-cn.md /XiangShan/ready-to-run /XiangShan/scripts/autorun/common/local_config.py /XiangShan/scripts/autorun/common/simulator_task_goback.py /XiangShan/scripts/autorun/common/task_tree_go_back.py /XiangShan/scripts/autorun/config.py /XiangShan/scripts/autorun/run.py /XiangShan/scripts/coverage/coverage.py /XiangShan/scripts/coverage/statistics.py /XiangShan/scripts/statistics.py /XiangShan/scripts/utils/lock-emu.c /XiangShan/scripts/xiangshan.py /XiangShan/src/main/resources/vsrc/regfile_160x64_10w16r_sim.v /XiangShan/src/main/scala/bus/tilelink/Arbiter.scala /XiangShan/src/main/scala/bus/tilelink/Metadata.scala /XiangShan/src/main/scala/bus/tilelink/TLUtilities.scala /XiangShan/src/main/scala/bus/tilelink/TileLink.scala /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/device/AXI4IntrGenerator.scala /XiangShan/src/main/scala/device/AXI4Keyboard.scala /XiangShan/src/main/scala/device/AXI4Plic.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4SlaveModule.scala /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/AXI4VGA.scala /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/difftest/Difftest.scala /XiangShan/src/main/scala/gpu/GPU.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/CircularQueuePtr.scala /XiangShan/src/main/scala/utils/DataDontCareNode.scala /XiangShan/src/main/scala/utils/DataModuleTemplate.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/ECC.scala /XiangShan/src/main/scala/utils/ExcitingUtils.scala /XiangShan/src/main/scala/utils/ExtractVerilogModules.scala /XiangShan/src/main/scala/utils/FlushableQueue.scala /XiangShan/src/main/scala/utils/GTimer.scala /XiangShan/src/main/scala/utils/Hold.scala /XiangShan/src/main/scala/utils/LFSR64.scala /XiangShan/src/main/scala/utils/LatencyPipe.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/LookupTree.scala /XiangShan/src/main/scala/utils/MIMOQueue.scala /XiangShan/src/main/scala/utils/Misc.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/utils/PerfCounterUtils.scala /XiangShan/src/main/scala/utils/PipelineConnect.scala /XiangShan/src/main/scala/utils/PriorityMuxDefault.scala /XiangShan/src/main/scala/utils/PriorityMuxGen.scala /XiangShan/src/main/scala/utils/RegMap.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/utils/ResetGen.scala /XiangShan/src/main/scala/utils/SRAMTemplate.scala /XiangShan/src/main/scala/utils/StopWatch.scala /XiangShan/src/main/scala/utils/TLDump.scala /XiangShan/src/main/scala/utils/TLIgnoreNode.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/PMA.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSDts.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FloatBlock.scala /XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Instructions.scala /XiangShan/src/main/scala/xiangshan/backend/decode/StoreSet.scala /XiangShan/src/main/scala/xiangshan/backend/decode/WaitTable.scala predecode.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/IndexMapping.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wb.scala /XiangShan/src/main/scala/xiangshan/backend/ftq/Ftq.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/issue/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/PayloadArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SelectPolicy.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/WakeupQueue.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/AMOALU.scala /XiangShan/src/main/scala/xiangshan/cache/AtomicsReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/DCache.scala /XiangShan/src/main/scala/xiangshan/cache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/ICache.scala /XiangShan/src/main/scala/xiangshan/cache/ICacheMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/InstrUncache.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/L1plusCache.scala /XiangShan/src/main/scala/xiangshan/cache/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/Mem.scala /XiangShan/src/main/scala/xiangshan/cache/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/Probe.scala /XiangShan/src/main/scala/xiangshan/cache/StoreReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/Uncache.scala /XiangShan/src/main/scala/xiangshan/cache/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLBMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PTW.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/L1plusPrefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/L2Prefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/Prefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/StreamPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/MaskedDataModule.scala /XiangShan/src/main/scala/xiangshan/mem/MemUtils.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xstransforms/PrintControl.scala /XiangShan/src/main/scala/xstransforms/PrintModuleName.scala /XiangShan/src/test/csrc/common/axi4.cpp /XiangShan/src/test/csrc/common/axi4.h /XiangShan/src/test/csrc/common/common.cpp /XiangShan/src/test/csrc/common/common.h /XiangShan/src/test/csrc/common/compress.cpp /XiangShan/src/test/csrc/common/compress.h /XiangShan/src/test/csrc/common/device.cpp /XiangShan/src/test/csrc/common/device.h /XiangShan/src/test/csrc/common/flash.cpp /XiangShan/src/test/csrc/common/flash.h /XiangShan/src/test/csrc/common/keyboard.cpp /XiangShan/src/test/csrc/common/macro.h /XiangShan/src/test/csrc/common/ram.cpp /XiangShan/src/test/csrc/common/ram.h /XiangShan/src/test/csrc/common/sdcard.cpp /XiangShan/src/test/csrc/common/sdcard.h /XiangShan/src/test/csrc/common/uart.cpp /XiangShan/src/test/csrc/common/vga.cpp /XiangShan/src/test/csrc/difftest/difftest.cpp /XiangShan/src/test/csrc/difftest/difftest.h /XiangShan/src/test/csrc/difftest/goldenmem.cpp /XiangShan/src/test/csrc/difftest/goldenmem.h /XiangShan/src/test/csrc/difftest/interface.cpp /XiangShan/src/test/csrc/difftest/interface.h /XiangShan/src/test/csrc/difftest/nemuproxy.cpp /XiangShan/src/test/csrc/difftest/nemuproxy.h /XiangShan/src/test/csrc/difftest/ref.cpp /XiangShan/src/test/csrc/difftest/ref.h /XiangShan/src/test/csrc/vcs/main.cpp /XiangShan/src/test/csrc/verilator/emu.cpp /XiangShan/src/test/csrc/verilator/emu.h /XiangShan/src/test/csrc/verilator/main.cpp /XiangShan/src/test/csrc/verilator/snapshot.cpp /XiangShan/src/test/csrc/verilator/snapshot.h /XiangShan/src/test/scala/cache/CacheTest.scala /XiangShan/src/test/scala/cache/L1DTest/CoreAgent.scala /XiangShan/src/test/scala/cache/L1DTest/CoreTransatcion.scala /XiangShan/src/test/scala/cache/L1DTest/L1DTest.scala /XiangShan/src/test/scala/cache/L1plusCacheTest.scala /XiangShan/src/test/scala/cache/L2CacheNonInclusiveGetTest.scala /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/cache/ReplaceTest.scala /XiangShan/src/test/scala/cache/TLCTest/BigIntUtil.scala /XiangShan/src/test/scala/cache/TLCTest/FixedBlockFuzzer.scala /XiangShan/src/test/scala/cache/TLCTest/TLCAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTest.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTransaction.scala /XiangShan/src/test/scala/cache/TLCTest/TLMasterMMIO.scala /XiangShan/src/test/scala/cache/TLCTest/TLSlaveMMIO.scala /XiangShan/src/test/scala/cache/TLCTest/TLULAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLULMMIO.scala /XiangShan/src/test/scala/cache/UnalignedGetTest.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala /XiangShan/src/test/scala/xiangshan/testutils/PartialDecoupledDriver.scala /XiangShan/src/test/scala/xiangshan/testutils/TestCaseGenerator.scala /XiangShan/src/test/testcase/Makefile /XiangShan/src/test/testcase/tests/double-loop.c /XiangShan/src/test/testcase/tests/nested-loop.c /XiangShan/src/test/vsrc/common/assert.v /XiangShan/src/test/vsrc/common/difftest.v /XiangShan/src/test/vsrc/common/ram.v /XiangShan/src/test/vsrc/common/ref.v /XiangShan/src/test/vsrc/vcs/top.v /XiangShan/tools/readmemh/Makefile /XiangShan/tools/readmemh/gen-treadle-readmemh.c /XiangShan/tools/readmemh/groupby-4byte.c /XiangShan/tools/readmemh/split-readmemh.c /XiangShan/vcs.mk /XiangShan/verilator.mk /XiangShan/xs-arch-simple.svg
c6d43980	04-Jun-2021	Lemover <[email protected]>	Add MulanPSL-2.0 License (#824) In this commit, we add License for XiangShan project. /XiangShan/.github/workflows/check-usage.sh /XiangShan/.github/workflows/emu.yml /XiangShan/.gitignore /XiangShan/.gitmodules /XiangShan/.mill-jvm-opts /XiangShan/.mill-version /XiangShan/LICENSE /XiangShan/Makefile /XiangShan/README.md /XiangShan/api-config-chipsalliance /XiangShan/berkeley-hardfloat /XiangShan/block-inclusivecache-sifive /XiangShan/build.sc /XiangShan/chiseltest /XiangShan/debug/Makefile /XiangShan/debug/cputest.sh /XiangShan/debug/env.sh /XiangShan/debug/perf_sbuffer.sh /XiangShan/debug/sc_stat.sh /XiangShan/ready-to-run/bbl.bin /XiangShan/ready-to-run/linux.bin /XiangShan/ready-to-run/microbench.bin /XiangShan/ready-to-run/riscv64-nemu-interpreter-so /XiangShan/rocket-chip /XiangShan/scripts/autorun/README.md /XiangShan/scripts/autorun/common/__init__.py /XiangShan/scripts/autorun/common/local_config.py /XiangShan/scripts/autorun/common/simulator_task_goback.py /XiangShan/scripts/autorun/common/task_tree_go_back.py /XiangShan/scripts/autorun/config.py /XiangShan/scripts/autorun/run.py /XiangShan/scripts/coverage/coverage.py /XiangShan/scripts/coverage/statistics.py /XiangShan/scripts/statistics.py /XiangShan/scripts/utils/lock-emu.c /XiangShan/scripts/vlsi_mem_gen /XiangShan/scripts/xiangshan.py /XiangShan/src/main/resources/vsrc/regfile_160x64_10w16r_sim.v /XiangShan/src/main/scala/bus/tilelink/Arbiter.scala /XiangShan/src/main/scala/bus/tilelink/Metadata.scala /XiangShan/src/main/scala/bus/tilelink/TLUtilities.scala /XiangShan/src/main/scala/bus/tilelink/TileLink.scala /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/device/AXI4IntrGenerator.scala /XiangShan/src/main/scala/device/AXI4Keyboard.scala /XiangShan/src/main/scala/device/AXI4Plic.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4SlaveModule.scala /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/AXI4VGA.scala /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/difftest/Difftest.scala /XiangShan/src/main/scala/gpu/GPU.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/CircularQueuePtr.scala /XiangShan/src/main/scala/utils/DataDontCareNode.scala /XiangShan/src/main/scala/utils/DataModuleTemplate.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/ECC.scala /XiangShan/src/main/scala/utils/ExcitingUtils.scala /XiangShan/src/main/scala/utils/ExtractVerilogModules.scala /XiangShan/src/main/scala/utils/FlushableQueue.scala /XiangShan/src/main/scala/utils/GTimer.scala /XiangShan/src/main/scala/utils/Hold.scala /XiangShan/src/main/scala/utils/LFSR64.scala /XiangShan/src/main/scala/utils/LatencyPipe.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/LookupTree.scala /XiangShan/src/main/scala/utils/MIMOQueue.scala /XiangShan/src/main/scala/utils/Misc.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/utils/PerfCounterUtils.scala /XiangShan/src/main/scala/utils/PipelineConnect.scala /XiangShan/src/main/scala/utils/PriorityMuxDefault.scala /XiangShan/src/main/scala/utils/PriorityMuxGen.scala /XiangShan/src/main/scala/utils/RegMap.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/utils/ResetGen.scala /XiangShan/src/main/scala/utils/SRAMTemplate.scala /XiangShan/src/main/scala/utils/StopWatch.scala /XiangShan/src/main/scala/utils/TLDump.scala /XiangShan/src/main/scala/utils/TLIgnoreNode.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/PMA.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSDts.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FloatBlock.scala /XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Instructions.scala /XiangShan/src/main/scala/xiangshan/backend/decode/StoreSet.scala /XiangShan/src/main/scala/xiangshan/backend/decode/WaitTable.scala predecode.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/IndexMapping.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wb.scala /XiangShan/src/main/scala/xiangshan/backend/ftq/Ftq.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/issue/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/PayloadArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SelectPolicy.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/WakeupQueue.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/AMOALU.scala /XiangShan/src/main/scala/xiangshan/cache/AtomicsReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/DCache.scala /XiangShan/src/main/scala/xiangshan/cache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/ICache.scala /XiangShan/src/main/scala/xiangshan/cache/ICacheMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/InstrUncache.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/L1plusCache.scala /XiangShan/src/main/scala/xiangshan/cache/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/Mem.scala /XiangShan/src/main/scala/xiangshan/cache/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/PTW.scala /XiangShan/src/main/scala/xiangshan/cache/Probe.scala /XiangShan/src/main/scala/xiangshan/cache/StoreReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/Uncache.scala /XiangShan/src/main/scala/xiangshan/cache/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/L1plusPrefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/L2Prefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/Prefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/StreamPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/MaskedDataModule.scala /XiangShan/src/main/scala/xiangshan/mem/MemUtils.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xstransforms/PrintModuleName.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/csrc/common/axi4.cpp /XiangShan/src/test/csrc/common/axi4.h /XiangShan/src/test/csrc/common/common.cpp /XiangShan/src/test/csrc/common/common.h /XiangShan/src/test/csrc/common/compress.cpp /XiangShan/src/test/csrc/common/compress.h /XiangShan/src/test/csrc/common/device.cpp /XiangShan/src/test/csrc/common/device.h /XiangShan/src/test/csrc/common/flash.cpp /XiangShan/src/test/csrc/common/flash.h /XiangShan/src/test/csrc/common/keyboard.cpp /XiangShan/src/test/csrc/common/macro.h /XiangShan/src/test/csrc/common/ram.cpp /XiangShan/src/test/csrc/common/ram.h /XiangShan/src/test/csrc/common/sdcard.cpp /XiangShan/src/test/csrc/common/sdcard.h /XiangShan/src/test/csrc/common/uart.cpp /XiangShan/src/test/csrc/common/vga.cpp /XiangShan/src/test/csrc/difftest/difftest.cpp /XiangShan/src/test/csrc/difftest/difftest.h /XiangShan/src/test/csrc/difftest/goldenmem.cpp /XiangShan/src/test/csrc/difftest/goldenmem.h /XiangShan/src/test/csrc/difftest/interface.cpp /XiangShan/src/test/csrc/difftest/interface.h /XiangShan/src/test/csrc/difftest/nemuproxy.cpp /XiangShan/src/test/csrc/difftest/nemuproxy.h /XiangShan/src/test/csrc/difftest/ref.cpp /XiangShan/src/test/csrc/difftest/ref.h /XiangShan/src/test/csrc/vcs/main.cpp /XiangShan/src/test/csrc/verilator/emu.cpp /XiangShan/src/test/csrc/verilator/emu.h /XiangShan/src/test/csrc/verilator/main.cpp /XiangShan/src/test/csrc/verilator/snapshot.cpp /XiangShan/src/test/csrc/verilator/snapshot.h /XiangShan/src/test/scala/cache/CacheTest.scala /XiangShan/src/test/scala/cache/L1DTest/CoreAgent.scala /XiangShan/src/test/scala/cache/L1DTest/CoreTransatcion.scala /XiangShan/src/test/scala/cache/L1DTest/L1DTest.scala /XiangShan/src/test/scala/cache/L1plusCacheTest.scala /XiangShan/src/test/scala/cache/L2CacheNonInclusiveGetTest.scala /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/cache/ReplaceTest.scala /XiangShan/src/test/scala/cache/TLCTest/BigIntUtil.scala /XiangShan/src/test/scala/cache/TLCTest/FixedBlockFuzzer.scala /XiangShan/src/test/scala/cache/TLCTest/TLCAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTest.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTransaction.scala /XiangShan/src/test/scala/cache/TLCTest/TLMasterMMIO.scala /XiangShan/src/test/scala/cache/TLCTest/TLSlaveMMIO.scala /XiangShan/src/test/scala/cache/TLCTest/TLULAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLULMMIO.scala /XiangShan/src/test/scala/cache/UnalignedGetTest.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala /XiangShan/src/test/scala/xiangshan/testutils/PartialDecoupledDriver.scala /XiangShan/src/test/scala/xiangshan/testutils/TestCaseGenerator.scala /XiangShan/src/test/testcase/Makefile /XiangShan/src/test/testcase/tests/double-loop.c /XiangShan/src/test/testcase/tests/nested-loop.c /XiangShan/src/test/vsrc/common/assert.v /XiangShan/src/test/vsrc/common/difftest.v /XiangShan/src/test/vsrc/common/ram.v /XiangShan/src/test/vsrc/common/ref.v /XiangShan/src/test/vsrc/vcs/top.v /XiangShan/timingScripts /XiangShan/tools/readmemh/Makefile /XiangShan/tools/readmemh/gen-treadle-readmemh.c /XiangShan/tools/readmemh/groupby-4byte.c /XiangShan/tools/readmemh/split-readmemh.c /XiangShan/vcs.mk /XiangShan/verilator.mk
d077b118	05-Aug-2020	zhanglinjuan <[email protected]>	decoder/rvc: add rvc instructions /XiangShan/Makefile /XiangShan/build.sc /XiangShan/debug/Makefile /XiangShan/scripts/statistics.py /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/noop/EXU.scala /XiangShan/src/main/scala/noop/NOOPTrap.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Parameters.scala /XiangShan/src/main/scala/top/TopMain.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/utils/PriorityMuxDefault.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVC.scala predecode.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/device.cpp /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/csrc/snapshot.h /XiangShan/src/test/csrc/uart.cpp /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala /XiangShan/src/test/scala/xiangshan/frontend/PDtest.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala
68eeafa8	31-Jul-2020	zhangfw <[email protected]>	Predecode: replace old PDecode /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile /XiangShan/debug/Makefile /XiangShan/scripts/statistics.py /XiangShan/src/main/scala/bus/simplebus/Crossbar.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVZifencei.scala predecode.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/btb.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/monitor.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/csrc/vga.cpp /XiangShan/src/test/scala/IFUtest/PDtest.scala /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala /XiangShan/src/test/testcase/Makefile /XiangShan/src/test/testcase/tests/double-loop.c /XiangShan/src/test/testcase/tests/nested-loop.c
f498737c	21-Jul-2020	zhangfw <[email protected]>	PDecode:fix bug /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala predecode.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/frontend/PDecode.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/scala/IFUtest/PDtest.scala
66314a38	19-Jul-2020	zhangfw <[email protected]>	PDecode: remote Sbb, add RVC /XiangShan/.github/workflows/emu.yml /XiangShan/.gitignore /XiangShan/Makefile /XiangShan/README.md /XiangShan/build.sbt /XiangShan/build.sc /XiangShan/debug/.gitignore /XiangShan/debug/Makefile /XiangShan/fpga/Makefile /XiangShan/fpga/Makefile.check /XiangShan/fpga/board/axu3cg/bd/prm.tcl /XiangShan/fpga/board/axu3cg/constr/hdmi.xdc /XiangShan/fpga/board/axu3cg/mk.tcl /XiangShan/fpga/board/axu3cg/rtl/addr_mapper.v /XiangShan/fpga/board/axu3cg/rtl/hdmi/i2c_config.v /XiangShan/fpga/board/axu3cg/rtl/hdmi/i2c_master_bit_ctrl.v /XiangShan/fpga/board/axu3cg/rtl/hdmi/i2c_master_byte_ctrl.v /XiangShan/fpga/board/axu3cg/rtl/hdmi/i2c_master_defines.v /XiangShan/fpga/board/axu3cg/rtl/hdmi/i2c_master_top.v /XiangShan/fpga/board/axu3cg/rtl/hdmi/timescale.v /XiangShan/fpga/board/axu3cg/rtl/system_top.v /XiangShan/fpga/board/common.tcl /XiangShan/fpga/board/ultraZ/bd/prm.tcl /XiangShan/fpga/board/ultraZ/constr/constr.xdc /XiangShan/fpga/board/ultraZ/mk.tcl /XiangShan/fpga/board/ultraZ/rtl/addr_mapper.v /XiangShan/fpga/board/ultraZ/rtl/system_top.v /XiangShan/fpga/board/zedboard/bd/prm.tcl /XiangShan/fpga/board/zedboard/constr/constr.xdc /XiangShan/fpga/board/zedboard/constr/vga.xdc /XiangShan/fpga/board/zedboard/mk.tcl /XiangShan/fpga/board/zedboard/rtl/addr_mapper.v /XiangShan/fpga/board/zedboard/rtl/system_top.v /XiangShan/fpga/boot/.gitignore /XiangShan/fpga/boot/README.md /XiangShan/fpga/boot/axu3cg/u-boot.elf /XiangShan/fpga/boot/bootgen-zynq.bif /XiangShan/fpga/boot/bootgen-zynqmp.bif /XiangShan/fpga/boot/bug-list.md /XiangShan/fpga/boot/mk.tcl /XiangShan/fpga/lib/include/axi.vh /XiangShan/fpga/noop.tcl /XiangShan/fpga/resource/ddr-loader/ddr-loader.c /XiangShan/project/build.properties /XiangShan/scalastyle-config.xml /XiangShan/scalastyle-test-config.xml /XiangShan/scripts/vlsi_mem_gen /XiangShan/src/main/scala/bus/axi4/AXI4.scala /XiangShan/src/main/scala/bus/axi4/Delayer.scala /XiangShan/src/main/scala/bus/simplebus/Crossbar.scala /XiangShan/src/main/scala/bus/simplebus/DistributedMem.scala /XiangShan/src/main/scala/bus/simplebus/SimpleBus.scala /XiangShan/src/main/scala/bus/simplebus/ToAXI4.scala /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/device/AXI4Keyboard.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4Slave.scala /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/AXI4VGA.scala /XiangShan/src/main/scala/fpu/Classify.scala /XiangShan/src/main/scala/fpu/F32toF64.scala /XiangShan/src/main/scala/fpu/F64toF32.scala /XiangShan/src/main/scala/fpu/FCMP.scala /XiangShan/src/main/scala/fpu/FMV.scala /XiangShan/src/main/scala/fpu/FPUSubModule.scala /XiangShan/src/main/scala/fpu/FloatToInt.scala /XiangShan/src/main/scala/fpu/IntToFloat.scala /XiangShan/src/main/scala/fpu/README.md /XiangShan/src/main/scala/fpu/RoundingUnit.scala /XiangShan/src/main/scala/fpu/divsqrt/DivSqrt.scala /XiangShan/src/main/scala/fpu/divsqrt/MantDivSqrt.scala /XiangShan/src/main/scala/fpu/divsqrt/OnTheFlyConv.scala /XiangShan/src/main/scala/fpu/divsqrt/SrtTable.scala /XiangShan/src/main/scala/fpu/fma/ArrayMultiplier.scala /XiangShan/src/main/scala/fpu/fma/FMA.scala /XiangShan/src/main/scala/fpu/fma/LZA.scala /XiangShan/src/main/scala/fpu/package.scala /XiangShan/src/main/scala/fpu/util/CarrySaveAdder.scala /XiangShan/src/main/scala/fpu/util/FPUDebug.scala /XiangShan/src/main/scala/fpu/util/ORTree.scala /XiangShan/src/main/scala/fpu/util/ShiftLeftJam.scala /XiangShan/src/main/scala/fpu/util/ShiftRightJam.scala /XiangShan/src/main/scala/gpu/GPU.scala /XiangShan/src/main/scala/noop/BPU.scala /XiangShan/src/main/scala/noop/Bundle.scala /XiangShan/src/main/scala/noop/Cache.scala /XiangShan/src/main/scala/noop/Decode.scala /XiangShan/src/main/scala/noop/EXU.scala /XiangShan/src/main/scala/noop/IDU1.scala /XiangShan/src/main/scala/noop/IDU2.scala /XiangShan/src/main/scala/noop/IFU.scala /XiangShan/src/main/scala/noop/ISU.scala /XiangShan/src/main/scala/noop/NOOP.scala /XiangShan/src/main/scala/noop/NOOPTrap.scala /XiangShan/src/main/scala/noop/TLB.scala /XiangShan/src/main/scala/noop/WBU.scala /XiangShan/src/main/scala/noop/fu/ALU.scala /XiangShan/src/main/scala/noop/fu/CSR.scala /XiangShan/src/main/scala/noop/fu/FPU.scala /XiangShan/src/main/scala/noop/fu/LSU.scala /XiangShan/src/main/scala/noop/fu/MDU.scala /XiangShan/src/main/scala/noop/fu/MOU.scala /XiangShan/src/main/scala/noop/isa/Priviledged.scala /XiangShan/src/main/scala/noop/isa/RVA.scala /XiangShan/src/main/scala/noop/isa/RVC.scala /XiangShan/src/main/scala/noop/isa/RVD.scala /XiangShan/src/main/scala/noop/isa/RVF.scala /XiangShan/src/main/scala/noop/isa/RVI.scala /XiangShan/src/main/scala/noop/isa/RVM.scala /XiangShan/src/main/scala/noop/isa/RVZicsr.scala /XiangShan/src/main/scala/noop/isa/RVZifencei.scala /XiangShan/src/main/scala/system/Coherence.scala /XiangShan/src/main/scala/system/Prefetcher.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/TopMain.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/Debug.scala /XiangShan/src/main/scala/utils/ExcitingUtils.scala /XiangShan/src/main/scala/utils/FlushableQueue.scala /XiangShan/src/main/scala/utils/GTimer.scala /XiangShan/src/main/scala/utils/Hold.scala /XiangShan/src/main/scala/utils/LFSR64.scala /XiangShan/src/main/scala/utils/LatencyPipe.scala /XiangShan/src/main/scala/utils/Lock.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/LookupTree.scala /XiangShan/src/main/scala/utils/MIMOQueue.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/utils/Pipeline.scala /XiangShan/src/main/scala/utils/PriorityMuxDefault.scala /XiangShan/src/main/scala/utils/RegMap.scala /XiangShan/src/main/scala/utils/SRAMTemplate.scala /XiangShan/src/main/scala/utils/StopWatch.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/XSTrap.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/Privileged.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVA.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVC.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVD.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVF.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVI.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVM.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVZicsr.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVZifencei.scala predecode.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchGen.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/RegfileReadPortGen.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/DivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fmac.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fmisc.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/I2f.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/PDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/btb.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/device.cpp /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/keyboard.cpp /XiangShan/src/test/csrc/macro.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/monitor.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/sdcard.cpp /XiangShan/src/test/csrc/uart.cpp /XiangShan/src/test/csrc/vga.cpp /XiangShan/src/test/scala/IFUtest/IFUtest.scala /XiangShan/src/test/scala/cache/CacheTest.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/AluTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala /XiangShan/src/test/scala/xiangshan/testutils/PartialDecoupledDriver.scala /XiangShan/src/test/scala/xiangshan/testutils/TestCaseGenerator.scala /XiangShan/src/test/vsrc/monitor.v /XiangShan/src/test/vsrc/ram.v /XiangShan/tools/readmemh/Makefile /XiangShan/tools/readmemh/gen-treadle-readmemh.c /XiangShan/tools/readmemh/groupby-4byte.c /XiangShan/tools/readmemh/split-readmemh.c