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Searched defs:debug (Results 1 – 12 of 12) sorted by relevance

/XiangShan/src/main/scala/utils/
H A DDebugIdentityNode.scala40 def debug(t: TLBundle, valid: Boolean = false): Unit ={ method
/XiangShan/src/main/scala/device/
H A DRocketDebugWrapper.scala43 val debug = LazyModule(new TLDebugModule(8)(p)) constant
/XiangShan/src/test/scala/xiangshan/backend/fu/
H A DVsetTop.scala23 val debug = new XSBundle() { constant
/XiangShan/src/main/scala/top/
H A DXSNoCTop.scala87 val debug = InModuleBody(debugIntNode.makeIOs()) constant
/XiangShan/src/main/scala/xiangshan/backend/
H A DBundles.scala735 val debug = new DebugBundle constant
756 val debug = new DebugBundle constant
965 val debug = new DebugBundle constant
/XiangShan/src/main/scala/xiangshan/frontend/
H A DnewRAS.scala152 val debug = new RASDebug constant
H A DBPU.scala53 val debug = true constant
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/
H A DInterruptFilter.scala603 val debug = Bool() constant
H A DNewCSR.scala395 val debug = RegEnable(intrMod.io.out.debug, false.B, intrMod.io.out.interruptVec.valid) constant
/XiangShan/src/main/scala/xiangshan/cache/mmu/
H A DMMUBundle.scala541 val debug = new Bundle { constant
577 val debug = new Bundle { constant
/XiangShan/src/main/scala/xiangshan/mem/pipeline/
H A DLoadUnit.scala60 val debug = new PerfDebugInfo constant
/XiangShan/src/main/scala/xiangshan/
H A DBundle.scala368 val debug = Input(Bool()) constant