| /XiangShan/src/main/scala/xiangshan/mem/lsqueue/ |
| H A D | FreeList.scala | 94 val offset = PopCount(freeReq.take(i)) constant
113 val offset = PopCount(io.allocateReq.take(i)) constant
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| H A D | LoadQueueRAR.scala | 156 val offset = PopCount(needEnqueue.take(w)) constant
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| H A D | LoadQueueRAW.scala | 138 val offset = PopCount(needEnqueue.take(w)) constant
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| H A D | LoadQueueUncache.scala | 384 val offset = PopCount(s2_enqueue.take(w)) constant
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| H A D | LoadQueueReplay.scala | 624 val offset = PopCount(newEnqueue.take(w)) constant
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| /XiangShan/src/main/scala/xiangshan/backend/fu/ |
| H A D | Jump.scala | 49 val offset = SignExt(imm, XLEN) constant
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| /XiangShan/src/main/scala/xiangshan/backend/datapath/ |
| H A D | PcTargetMem.scala | 54 val offset = io.toDataPath.fromDataPathFtqOffset(i) constant
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| /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/ |
| H A D | StdFreeList.scala | 40 val offset = if (i == 0) 0.U else PopCount(freeReqReg.take(i)) constant
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| /XiangShan/src/main/scala/xiangshan/backend/decode/ |
| H A D | DecodeUnitComp.scala | 45 var offset = 1 << (emul - lmul) variable
52 var offset = 1 << (lmul - emul) variable
65 var offset = genCsBundle_VEC_INDEXED_LDST(lmul, emul, uopIdx) variable
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| /XiangShan/src/main/scala/xiangshan/mem/sbuffer/ |
| H A D | StorePrefetchBursts.scala | 43 val offset = log2Up(dcacheParameters.blockBytes) constant
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| /XiangShan/src/main/scala/xiangshan/backend/ |
| H A D | VecExcpDataMergeModule.scala | 591 val offset = UInt(tailZeroBit.W) constant
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| /XiangShan/src/main/scala/xiangshan/mem/vector/ |
| H A D | VMergeBuffer.scala | 144 val offset = PopCount(needEnqueue.take(i)) constant
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| H A D | VSplit.scala | 300 val offset = PopCount(needEnqueue) constant
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| /XiangShan/src/main/scala/xiangshan/mem/prefetch/ |
| H A D | SMSPrefetcher.scala | 83 val offset = log2Up(dcacheParameters.blockBytes) constant
88 val offset = log2Up(REGION_SIZE) constant
134 val offset = log2Up(REGION_SIZE) constant
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| /XiangShan/src/main/scala/xiangshan/frontend/ |
| H A D | FTB.scala | 47 val offset = UInt(log2Ceil(PredictWidth).W) constant
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| H A D | ITTAGE.scala | 78 val offset = UInt(TargetOffsetBits.W) constant
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| H A D | FrontendBundle.scala | 506 val offset = UInt(instOffsetBits.W) constant
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| H A D | NewFtq.scala | 189 val offset = Output(UInt(log2Ceil(PredictWidth).W)) constant
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