| /XiangShan/src/main/scala/xiangshan/backend/fu/ |
| H A D | Bku.scala | 29 val src = Input(UInt(XLEN.W)) constant
85 val src = Vec(2, Input(UInt(XLEN.W))) constant
127 val src = Vec(2, Input(UInt(XLEN.W))) constant
153 val src = Input(UInt(XLEN.W)) constant
190 val src = Vec(2, Input(UInt(XLEN.W))) constant
298 val src = Vec(2, Input(UInt(XLEN.W))) constant
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| H A D | Branch.scala | 27 val src = Vec(2, Input(UInt(XLEN.W))) constant
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| H A D | Alu.scala | 27 val src = Vec(2, Input(UInt(XLEN.W))) constant
39 val src = Vec(2, Input(UInt(XLEN.W))) constant
101 val src = Input(UInt(XLEN.W)) constant
198 val src = Vec(2, Input(UInt(XLEN.W))) constant
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| H A D | Jump.scala | 36 val src = Input(UInt(XLEN.W)) constant
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| H A D | FunctionUnit.scala | 58 val src = Vec(3, UInt(len.W)) constant
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| H A D | FuncUnit.scala | 56 val src = MixedVec(cfg.genSrcDataVec) constant
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| H A D | SRT16Divider.scala | 41 val src = Vec(2, Input(UInt(len.W))) constant
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| H A D | SRT4Divider.scala | 36 val src = Vec(2, Input(UInt(len.W))) constant
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| /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/ |
| H A D | FliTable.scala | 8 val src = IO(Input(UInt(5.W))) constant
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| H A D | FPUSubModule.scala | 35 val src = Vec(3, UInt(64.W)) constant
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| /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/ |
| H A D | MulUnit.scala | 18 val src = io.in.bits.data.src constant
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| H A D | VCVT.scala | 185 val src = Input(Vec(vlen / xlen, UInt(xlen.W))) constant
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| /XiangShan/src/main/scala/xiangshan/backend/decode/ |
| H A D | UopInfoGen.scala | 38 val src = IO(Input(UInt(5.W))) constant
57 val src = IO(Input(UInt(7.W))) constant
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| H A D | DecodeUnitComp.scala | 39 val src = IO(Input(UInt(4.W))) constant
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| /XiangShan/src/main/scala/xiangshan/backend/ |
| H A D | Bundles.scala | 603 val src = Vec(params.numRegSrc, UInt(params.srcDataBitsMax.W)) constant
945 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) constant
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| /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/ |
| H A D | NewCSR.scala | 79 val src = UInt(64.W) constant
|