Searched hist:"8795 ffc00d922e6e6cde93b1027e9f79782b0564" (Results 1 – 4 of 4) sorted by relevance
| /XiangShan/src/main/scala/xiangshan/frontend/ |
| H A D | WrBypass.scala | diff 8795ffc00d922e6e6cde93b1027e9f79782b0564 Thu Apr 10 04:44:14 CEST 2025 Sam Castleberry <[email protected]> feat: move frontend SRAM read-write conflict handling to SRAMTemplate (#4445)
Hello, this change set is to remove the SRAM read-write conflict
handling logic in the frontend, after OpenXiangShan/Utility#110 has been
merged, which adds this logic to the SRAMTemplate. See that pull request
and also #4242 for more context.
After this change, I see microbench IPC change 1.397 -> 1.413 and
coremark IPC change 2.136 -> 2.147. The branch mispredictions also
decreased slightly in both.
This probably cannot be merged automatically, since the utility
submodule should point to the new revision after merging instead of the
revision in my branch.
Thanks, Sam
|
| H A D | SC.scala | diff 8795ffc00d922e6e6cde93b1027e9f79782b0564 Thu Apr 10 04:44:14 CEST 2025 Sam Castleberry <[email protected]> feat: move frontend SRAM read-write conflict handling to SRAMTemplate (#4445)
Hello, this change set is to remove the SRAM read-write conflict
handling logic in the frontend, after OpenXiangShan/Utility#110 has been
merged, which adds this logic to the SRAMTemplate. See that pull request
and also #4242 for more context.
After this change, I see microbench IPC change 1.397 -> 1.413 and
coremark IPC change 2.136 -> 2.147. The branch mispredictions also
decreased slightly in both.
This probably cannot be merged automatically, since the utility
submodule should point to the new revision after merging instead of the
revision in my branch.
Thanks, Sam
|
| H A D | Tage.scala | diff 8795ffc00d922e6e6cde93b1027e9f79782b0564 Thu Apr 10 04:44:14 CEST 2025 Sam Castleberry <[email protected]> feat: move frontend SRAM read-write conflict handling to SRAMTemplate (#4445)
Hello, this change set is to remove the SRAM read-write conflict
handling logic in the frontend, after OpenXiangShan/Utility#110 has been
merged, which adds this logic to the SRAMTemplate. See that pull request
and also #4242 for more context.
After this change, I see microbench IPC change 1.397 -> 1.413 and
coremark IPC change 2.136 -> 2.147. The branch mispredictions also
decreased slightly in both.
This probably cannot be merged automatically, since the utility
submodule should point to the new revision after merging instead of the
revision in my branch.
Thanks, Sam
|
| /XiangShan/ |
| H A D | build.sc | diff 8795ffc00d922e6e6cde93b1027e9f79782b0564 Thu Apr 10 04:44:14 CEST 2025 Sam Castleberry <[email protected]> feat: move frontend SRAM read-write conflict handling to SRAMTemplate (#4445)
Hello, this change set is to remove the SRAM read-write conflict
handling logic in the frontend, after OpenXiangShan/Utility#110 has been
merged, which adds this logic to the SRAMTemplate. See that pull request
and also #4242 for more context.
After this change, I see microbench IPC change 1.397 -> 1.413 and
coremark IPC change 2.136 -> 2.147. The branch mispredictions also
decreased slightly in both.
This probably cannot be merged automatically, since the utility
submodule should point to the new revision after merging instead of the
revision in my branch.
Thanks, Sam
|