History log of /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala (Results 251 – 275 of 328)
Revision Date Author Comments
# dc649fbb 01-Feb-2021 Yinan Xu <[email protected]>

Merge remote-tracking branch 'origin/linux-debug' into opt-exception


# a31b14cd 31-Jan-2021 LinJiawei <[email protected]>

CtrlBlock: send exception flush to mem block after a 'RegNext'


# 3a474d38 30-Jan-2021 Yinan Xu <[email protected]>

roq: rename RoqExceptionInfo to ExceptionInfo


# 282a07b1 29-Jan-2021 LinJiawei <[email protected]>

CtrlBlock: fix flush logic


# ac870c74 28-Jan-2021 LinJiawei <[email protected]>

Merge remote-tracking branch 'origin/master' into ftq


# ac5a5d53 28-Jan-2021 LinJiawei <[email protected]>

CSR: mark MRet as a 'flushPipe'


# 9ed972ad 28-Jan-2021 LinJiawei <[email protected]>

CtrlBlock: send exception pc to csr one cycle later


# c32387e4 28-Jan-2021 wangkaifan <[email protected]>

Merge branch 'dual-stable' into dual-dev


# 37459b99 28-Jan-2021 LinJiawei <[email protected]>

Merge remote-tracking branch 'origin/opt-exception' into ftq


# 8f77f081 28-Jan-2021 Yinan Xu <[email protected]>

Merge remote-tracking branch 'origin/master' into opt-exception


# b1c52bdf 27-Jan-2021 wangkaifan <[email protected]>

Merge branch 'master' of https://github.com/RISCVERS/XiangShan into dual-stable


# 54bc08ad 27-Jan-2021 wangkaifan <[email protected]>

misc: optimize trap info transition for dual-core


# 76523708 27-Jan-2021 Yinan Xu <[email protected]>

Merge pull request #496 from RISCVERS/opt-memblock

Lsq, Roq: ld/st commit logic refactor


# 6886802e 27-Jan-2021 LinJiawei <[email protected]>

Merge remote-tracking branch 'origin/master' into ftq


# 07635e87 27-Jan-2021 wangkaifan <[email protected]>

difftest: wire out load instr info from core to enhance difftest


# 10aac6e7 26-Jan-2021 William Wang <[email protected]>

Lsq, Roq: ld/st commit logic refactor


# f7f707b0 26-Jan-2021 LinJiawei <[email protected]>

fix perf print, enable perf by default


# aa0e2ba9 25-Jan-2021 LinJiawei <[email protected]>

Roq: block inst commit when a load replay happen


# 58225d66 25-Jan-2021 LinJiawei <[email protected]>

Merge remote-tracking branch 'origin/master' into ftq


# 7aa94463 25-Jan-2021 LinJiawei <[email protected]>

fix backend bugs


# a165bd69 25-Jan-2021 wangkaifan <[email protected]>

difftest: support dual-core difftest signal in-core
* should be compatible with single core difftest framework


# 2d7c7105 25-Jan-2021 Yinan Xu <[email protected]>

redirect: split conditional redirect and unconditional redirect


# 37e3a7b0 24-Jan-2021 LinJiawei <[email protected]>

fix cfiIndexValid bug


# 6060732c 24-Jan-2021 LinJiawei <[email protected]>

fix backend bugs


# 744c623c 22-Jan-2021 Lingrui98 <[email protected]>

ftq and all: now we can compile


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