Searched defs:node (Results 1 – 14 of 14) sorted by relevance
| /XiangShan/src/main/scala/utils/ |
| H A D | DataDontCareNode.scala | 27 val node = TLIdentityNode() constant
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| H A D | DebugIdentityNode.scala | 28 val node = TLIdentityNode() constant
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| /XiangShan/src/main/scala/device/TLPMA/ |
| H A D | TLPMA.scala | 20 val node = TLRegisterNode( constant
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| /XiangShan/src/main/scala/device/ |
| H A D | AXI4SlaveModule.scala | 36 val node = AXI4SlaveNode(Seq(AXI4SlavePortParameters( constant
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| H A D | TLTimer.scala | 31 val node = TLRegisterNode(address, device, beatBytes = 8) constant
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| H A D | AXI4VGA.scala | 139 val node = AXI4IdentityNode() constant
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| H A D | MemEncrypt.scala | 954 val node = AXI4AdapterNode( constant
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| /XiangShan/src/test/scala/top/ |
| H A D | SimMMIO.scala | 33 val node = AXI4MasterNode(List(edge.master)) constant
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| /XiangShan/src/main/scala/top/ |
| H A D | BusPerfMonitor.scala | 28 val node = TLAdapterNode() constant
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/ |
| H A D | CtrlUnit.scala | 67 val node: TLRegisterNode = TLRegisterNode( constant
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| /XiangShan/src/main/scala/xiangshan/frontend/icache/ |
| H A D | ICacheCtrlUnit.scala | 58 val node: TLRegisterNode = TLRegisterNode( constant
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| /XiangShan/src/main/scala/xiangshan/cache/mmu/ |
| H A D | L2TLB.scala | 38 val node = TLClientNode(Seq(TLMasterPortParameters.v1( constant
959 val node = if (!useSoftPTW) TLIdentityNode() else null constant
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| /XiangShan/src/main/scala/xiangshan/ |
| H A D | L2Top.scala | 71 val node = buffers.map(_.node.asInstanceOf[TLNode]).reduce(_ :*=* _) constant
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| /XiangShan/src/main/scala/xiangshan/mem/ |
| H A D | MemBlock.scala | 202 …val node = new TLBufferNode(BufferParams.default, BufferParams.default, BufferParams.default, Buff… constant
223 …val node = new TLBufferNode(BufferParams.default, BufferParams.default, BufferParams.default, Buff… constant
235 …val node = new TLBufferNode(BufferParams.default, BufferParams.default, BufferParams.default, Buff… constant
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