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/linux-6.14.4/drivers/net/ethernet/microchip/sparx5/
Dsparx5_psfp.c2 /* Microchip Sparx5 Switch driver
23 static int sparx5_psfp_sf_get(struct sparx5 *sparx5, u32 *id) in sparx5_psfp_sf_get() argument
26 sparx5->data->consts->n_filters, id); in sparx5_psfp_sf_get()
29 static int sparx5_psfp_sf_put(struct sparx5 *sparx5, u32 id) in sparx5_psfp_sf_put() argument
32 sparx5->data->consts->n_filters, id); in sparx5_psfp_sf_put()
35 static int sparx5_psfp_sg_get(struct sparx5 *sparx5, u32 idx, u32 *id) in sparx5_psfp_sg_get() argument
38 sparx5->data->consts->n_gates, idx, id); in sparx5_psfp_sg_get()
41 static int sparx5_psfp_sg_put(struct sparx5 *sparx5, u32 id) in sparx5_psfp_sg_put() argument
44 sparx5->data->consts->n_gates, id); in sparx5_psfp_sg_put()
47 static int sparx5_psfp_fm_get(struct sparx5 *sparx5, u32 idx, u32 *id) in sparx5_psfp_fm_get() argument
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Dsparx5_mactable.c2 /* Microchip Sparx5 Switch driver
44 static int sparx5_mact_get_status(struct sparx5 *sparx5) in sparx5_mact_get_status() argument
46 return spx5_rd(sparx5, LRN_COMMON_ACCESS_CTRL); in sparx5_mact_get_status()
49 static int sparx5_mact_wait_for_completion(struct sparx5 *sparx5) in sparx5_mact_wait_for_completion() argument
54 sparx5, val, in sparx5_mact_wait_for_completion()
59 static void sparx5_mact_select(struct sparx5 *sparx5, in sparx5_mact_select() argument
76 spx5_wr(mach, sparx5, LRN_MAC_ACCESS_CFG_0); in sparx5_mact_select()
77 spx5_wr(macl, sparx5, LRN_MAC_ACCESS_CFG_1); in sparx5_mact_select()
80 int sparx5_mact_learn(struct sparx5 *sparx5, int pgid, in sparx5_mact_learn() argument
83 const struct sparx5_consts *consts = sparx5->data->consts; in sparx5_mact_learn()
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Dsparx5_fdma.c2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
36 struct sparx5 *sparx5 = fdma->priv; in sparx5_fdma_rx_dataptr_cb() local
37 struct sparx5_rx *rx = &sparx5->rx; in sparx5_fdma_rx_dataptr_cb()
51 static void sparx5_fdma_rx_activate(struct sparx5 *sparx5, struct sparx5_rx *rx) in sparx5_fdma_rx_activate() argument
56 spx5_wr(((u64)fdma->dma) & GENMASK(31, 0), sparx5, in sparx5_fdma_rx_activate()
58 spx5_wr(((u64)fdma->dma) >> 32, sparx5, in sparx5_fdma_rx_activate()
65 sparx5, FDMA_CH_CFG(fdma->channel_id)); in sparx5_fdma_rx_activate()
69 sparx5, in sparx5_fdma_rx_activate()
74 sparx5, FDMA_PORT_CTRL(0)); in sparx5_fdma_rx_activate()
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Dsparx5_sdlb.c2 /* Microchip Sparx5 Switch driver
28 u64 sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5) in sparx5_sdlb_clk_hz_get() argument
33 (sparx5_clk_period(sparx5->coreclock) / 100); in sparx5_sdlb_clk_hz_get()
38 static int sparx5_sdlb_pup_interval_get(struct sparx5 *sparx5, u32 max_token, in sparx5_sdlb_pup_interval_get() argument
43 clk_hz = sparx5_sdlb_clk_hz_get(sparx5); in sparx5_sdlb_pup_interval_get()
48 int sparx5_sdlb_pup_token_get(struct sparx5 *sparx5, u32 pup_interval, u64 rate) in sparx5_sdlb_pup_token_get() argument
55 clk_hz = sparx5_sdlb_clk_hz_get(sparx5); in sparx5_sdlb_pup_token_get()
60 static void sparx5_sdlb_group_disable(struct sparx5 *sparx5, u32 group) in sparx5_sdlb_group_disable() argument
63 ANA_AC_SDLB_PUP_CTRL_PUP_ENA, sparx5, in sparx5_sdlb_group_disable()
67 static void sparx5_sdlb_group_enable(struct sparx5 *sparx5, u32 group) in sparx5_sdlb_group_enable() argument
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Dsparx5_main.h2 /* Microchip Sparx5 Switch driver
139 struct sparx5;
211 struct sparx5 *sparx5; member
253 struct sparx5 *sparx5; member
334 u32 (*get_port_dev_index)(struct sparx5 *sparx5, int port);
335 u32 (*get_port_dev_bit)(struct sparx5 *sparx5, int port);
338 int (*set_port_mux)(struct sparx5 *sparx5, struct sparx5_port *port,
342 int (*dsm_calendar_calc)(struct sparx5 *sparx5, u32 taxi,
346 int (*fdma_init)(struct sparx5 *sparx5);
347 int (*fdma_deinit)(struct sparx5 *sparx5);
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Dsparx5_ptp.c2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
25 static u64 sparx5_ptp_get_1ppm(struct sparx5 *sparx5) in sparx5_ptp_get_1ppm() argument
35 switch (sparx5->coreclock) { in sparx5_ptp_get_1ppm()
56 static u64 sparx5_ptp_get_nominal_value(struct sparx5 *sparx5) in sparx5_ptp_get_nominal_value() argument
60 switch (sparx5->coreclock) { in sparx5_ptp_get_nominal_value()
85 struct sparx5 *sparx5 = port->sparx5; in sparx5_ptp_hwtstamp_set() local
93 if (test_bit(port->portno, sparx5->bridge_mask)) in sparx5_ptp_hwtstamp_set()
134 mutex_lock(&sparx5->ptp_lock); in sparx5_ptp_hwtstamp_set()
135 phc = &sparx5->phc[SPARX5_PHC_PORT]; in sparx5_ptp_hwtstamp_set()
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Dsparx5_vlan.c2 /* Microchip Sparx5 Switch driver
10 static int sparx5_vlant_set_mask(struct sparx5 *sparx5, u16 vid) in sparx5_vlant_set_mask() argument
15 bitmap_to_arr32(mask, sparx5->vlan_mask[vid], SPX5_PORTS); in sparx5_vlant_set_mask()
18 spx5_wr(mask[0], sparx5, ANA_L3_VLAN_MASK_CFG(vid)); in sparx5_vlant_set_mask()
19 if (is_sparx5(sparx5)) { in sparx5_vlant_set_mask()
20 spx5_wr(mask[1], sparx5, ANA_L3_VLAN_MASK_CFG1(vid)); in sparx5_vlant_set_mask()
21 spx5_wr(mask[2], sparx5, ANA_L3_VLAN_MASK_CFG2(vid)); in sparx5_vlant_set_mask()
27 void sparx5_vlan_init(struct sparx5 *sparx5) in sparx5_vlan_init() argument
33 sparx5, in sparx5_vlan_init()
40 sparx5, in sparx5_vlan_init()
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Dsparx5_main.c2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
215 bool is_sparx5(struct sparx5 *sparx5) in is_sparx5() argument
217 switch (sparx5->target_ct) { in is_sparx5()
234 static void sparx5_init_features(struct sparx5 *sparx5) in sparx5_init_features() argument
236 switch (sparx5->target_ct) { in sparx5_init_features()
256 sparx5->features = (SPX5_FEATURE_PSFP | SPX5_FEATURE_PTP); in sparx5_init_features()
263 bool sparx5_has_feature(struct sparx5 *sparx5, enum sparx5_feature feature) in sparx5_has_feature() argument
265 return sparx5->features & feature; in sparx5_has_feature()
268 static int sparx5_create_targets(struct sparx5 *sparx5) in sparx5_create_targets() argument
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Dsparx5_mirror.c2 /* Microchip Sparx5 Switch driver
24 static u64 sparx5_mirror_port_get(struct sparx5 *sparx5, u32 idx) in sparx5_mirror_port_get() argument
28 val = spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG(idx)); in sparx5_mirror_port_get()
30 if (is_sparx5(sparx5)) in sparx5_mirror_port_get()
31 val |= (u64)spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG1(idx)) << 32; in sparx5_mirror_port_get()
37 static void sparx5_mirror_port_add(struct sparx5 *sparx5, u32 idx, u32 portno) in sparx5_mirror_port_add() argument
45 return spx5_rmw(val, val, sparx5, ANA_AC_PROBE_PORT_CFG(idx)); in sparx5_mirror_port_add()
47 return spx5_rmw(val, val, sparx5, ANA_AC_PROBE_PORT_CFG1(idx)); in sparx5_mirror_port_add()
51 static void sparx5_mirror_port_del(struct sparx5 *sparx5, u32 idx, u32 portno) in sparx5_mirror_port_del() argument
59 return spx5_rmw(0, val, sparx5, ANA_AC_PROBE_PORT_CFG(idx)); in sparx5_mirror_port_del()
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Dsparx5_qos.c2 /* Microchip Sparx5 Switch driver
24 void sparx5_new_base_time(struct sparx5 *sparx5, const u32 cycle_time, in sparx5_new_base_time() argument
35 sparx5_ptp_gettime64(&sparx5->phc[SPARX5_PHC_PORT].info, &ts); in sparx5_new_base_time()
84 static u32 sparx5_lg_get_leak_time(struct sparx5 *sparx5, u32 layer, u32 group) in sparx5_lg_get_leak_time() argument
88 value = spx5_rd(sparx5, HSCH_HSCH_TIMER_CFG(layer, group)); in sparx5_lg_get_leak_time()
92 static void sparx5_lg_set_leak_time(struct sparx5 *sparx5, u32 layer, u32 group, in sparx5_lg_set_leak_time() argument
95 spx5_wr(HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(leak_time), sparx5, in sparx5_lg_set_leak_time()
99 static u32 sparx5_lg_get_first(struct sparx5 *sparx5, u32 layer, u32 group) in sparx5_lg_get_first() argument
103 value = spx5_rd(sparx5, HSCH_HSCH_LEAK_CFG(layer, group)); in sparx5_lg_get_first()
107 static u32 sparx5_lg_get_next(struct sparx5 *sparx5, u32 layer, u32 group, in sparx5_lg_get_next() argument
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Dsparx5_vcap_impl.c2 /* Microchip Sparx5 Switch driver VCAP implementation
6 * The Sparx5 Chip Register Model can be browsed at this location:
152 static void sparx5_vcap_type_err(struct sparx5 *sparx5, in sparx5_vcap_type_err() argument
161 static void sparx5_vcap_wait_super_update(struct sparx5 *sparx5) in sparx5_vcap_wait_super_update() argument
167 false, sparx5, VCAP_SUPER_CTRL); in sparx5_vcap_wait_super_update()
171 static void sparx5_vcap_wait_es0_update(struct sparx5 *sparx5) in sparx5_vcap_wait_es0_update() argument
177 false, sparx5, VCAP_ES0_CTRL); in sparx5_vcap_wait_es0_update()
181 static void sparx5_vcap_wait_es2_update(struct sparx5 *sparx5) in sparx5_vcap_wait_es2_update() argument
187 false, sparx5, VCAP_ES2_CTRL); in sparx5_vcap_wait_es2_update()
191 static void _sparx5_vcap_range_init(struct sparx5 *sparx5, in _sparx5_vcap_range_init() argument
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Dsparx5_port.c2 /* Microchip Sparx5 Switch driver
78 static int sparx5_get_dev2g5_status(struct sparx5 *sparx5, in sparx5_get_dev2g5_status() argument
87 value = spx5_rd(sparx5, DEV2G5_PCS1G_STICKY(portno)); in sparx5_get_dev2g5_status()
90 spx5_wr(value, sparx5, DEV2G5_PCS1G_STICKY(portno)); in sparx5_get_dev2g5_status()
93 value = spx5_rd(sparx5, DEV2G5_PCS1G_LINK_STATUS(portno)); in sparx5_get_dev2g5_status()
105 value = spx5_rd(sparx5, DEV2G5_PCS1G_ANEG_STATUS(portno)); in sparx5_get_dev2g5_status()
113 value = spx5_rd(sparx5, DEV2G5_PCS1G_ANEG_CFG(portno)); in sparx5_get_dev2g5_status()
121 static int sparx5_get_sfi_status(struct sparx5 *sparx5, in sparx5_get_sfi_status() argument
135 dev = sparx5_to_high_dev(sparx5, portno); in sparx5_get_sfi_status()
136 tinst = sparx5_port_dev_index(sparx5, portno); in sparx5_get_sfi_status()
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Dsparx5_netdev.c2 /* Microchip Sparx5 Switch driver
58 void sparx5_set_port_ifh(struct sparx5 *sparx5, void *ifh_hdr, u16 portno) in sparx5_set_port_ifh() argument
67 ifh_encode_bitfield(ifh_hdr, is_sparx5(sparx5) ? 16 : 17, 37, 5); in sparx5_set_port_ifh()
71 ifh_encode_bitfield(ifh_hdr, sparx5_get_pgid(sparx5, SPX5_PORT_CPU_0), in sparx5_set_port_ifh()
72 46, is_sparx5(sparx5) ? 7 : 6); in sparx5_set_port_ifh()
74 ifh_encode_bitfield(ifh_hdr, 124, is_sparx5(sparx5) ? 57 : 56, 7); in sparx5_set_port_ifh()
76 ifh_encode_bitfield(ifh_hdr, 1, is_sparx5(sparx5) ? 67 : 66, 1); in sparx5_set_port_ifh()
84 void sparx5_set_port_ifh_pdu_type(struct sparx5 *sparx5, void *ifh_hdr, in sparx5_set_port_ifh_pdu_type() argument
87 ifh_encode_bitfield(ifh_hdr, pdu_type, is_sparx5(sparx5) ? 191 : 190, in sparx5_set_port_ifh_pdu_type()
91 void sparx5_set_port_ifh_pdu_w16_offset(struct sparx5 *sparx5, void *ifh_hdr, in sparx5_set_port_ifh_pdu_w16_offset() argument
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Dsparx5_switchdev.c2 /* Microchip Sparx5 Switch driver
19 struct sparx5 *sparx5; member
35 struct sparx5 *sparx5 = port->sparx5; in sparx5_port_update_mcast_ip_flood() local
38 for (pgid = sparx5_get_pgid(sparx5, PGID_IPV4_MC_DATA); in sparx5_port_update_mcast_ip_flood()
39 pgid <= sparx5_get_pgid(sparx5, PGID_IPV6_MC_CTRL); pgid++) in sparx5_port_update_mcast_ip_flood()
46 struct sparx5 *sparx5 = port->sparx5; in sparx5_port_attr_bridge_flags() local
50 sparx5_get_pgid(sparx5, PGID_MC_FLOOD), in sparx5_port_attr_bridge_flags()
57 sparx5_get_pgid(sparx5, PGID_UC_FLOOD), in sparx5_port_attr_bridge_flags()
61 sparx5_get_pgid(sparx5, PGID_BCAST), in sparx5_port_attr_bridge_flags()
68 struct sparx5 *sparx5 = port->sparx5; in sparx5_attr_stp_state_set() local
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Dsparx5_packet.c2 /* Microchip Sparx5 Switch driver
23 void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp) in sparx5_xtr_flush() argument
26 spx5_wr(QS_XTR_FLUSH_FLUSH_SET(BIT(grp)), sparx5, QS_XTR_FLUSH); in sparx5_xtr_flush()
32 spx5_wr(0, sparx5, QS_XTR_FLUSH); in sparx5_xtr_flush()
35 void sparx5_ifh_parse(struct sparx5 *sparx5, u32 *ifh, struct frame_info *info) in sparx5_ifh_parse() argument
46 info->src_port = spx5_field_get(GENMASK(is_sparx5(sparx5) ? 7 : 6, 1), in sparx5_ifh_parse()
60 static void sparx5_xtr_grp(struct sparx5 *sparx5, u8 grp, bool byte_swap) in sparx5_xtr_grp() argument
73 ifh[i] = spx5_rd(sparx5, QS_XTR_RD(grp)); in sparx5_xtr_grp()
76 sparx5_ifh_parse(sparx5, ifh, &fi); in sparx5_xtr_grp()
79 port = fi.src_port < sparx5->data->consts->n_ports ? in sparx5_xtr_grp()
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Dsparx5_ethtool.c2 /* Microchip Sparx5 Switch driver
201 static void sparx5_get_queue_sys_stats(struct sparx5 *sparx5, int portno) in sparx5_get_queue_sys_stats() argument
208 portstats = &sparx5->stats[portno * sparx5->num_stats]; in sparx5_get_queue_sys_stats()
209 mutex_lock(&sparx5->queue_stats_lock); in sparx5_get_queue_sys_stats()
210 spx5_wr(XQS_STAT_CFG_STAT_VIEW_SET(portno), sparx5, XQS_STAT_CFG); in sparx5_get_queue_sys_stats()
214 sparx5_update_counter(stats, spx5_rd(sparx5, XQS_CNT(addr))); in sparx5_get_queue_sys_stats()
218 sparx5_update_counter(stats, spx5_rd(sparx5, XQS_CNT(addr))); in sparx5_get_queue_sys_stats()
222 sparx5_update_counter(stats, spx5_rd(sparx5, XQS_CNT(addr))); in sparx5_get_queue_sys_stats()
224 spx5_rd(sparx5, XQS_CNT(32))); in sparx5_get_queue_sys_stats()
226 spx5_rd(sparx5, XQS_CNT(272))); in sparx5_get_queue_sys_stats()
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Dsparx5_calendar.c2 /* Microchip Sparx5 Switch driver
37 static u32 sparx5_target_bandwidth(struct sparx5 *sparx5) in sparx5_target_bandwidth() argument
39 switch (sparx5->target_ct) { in sparx5_target_bandwidth()
118 enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5, u32 portno) in sparx5_get_port_cal_speed() argument
122 if (portno >= sparx5->data->consts->n_ports) { in sparx5_get_port_cal_speed()
125 sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0) || in sparx5_get_port_cal_speed()
127 sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_1)) { in sparx5_get_port_cal_speed()
131 sparx5_get_internal_port(sparx5, SPX5_PORT_VD0)) { in sparx5_get_port_cal_speed()
135 sparx5_get_internal_port(sparx5, SPX5_PORT_VD1)) { in sparx5_get_port_cal_speed()
139 sparx5_get_internal_port(sparx5, SPX5_PORT_VD2)) { in sparx5_get_port_cal_speed()
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Dsparx5_port.h2 /* Microchip Sparx5 Switch driver
48 static inline u32 sparx5_to_high_dev(struct sparx5 *sparx5, int port) in sparx5_to_high_dev() argument
50 const struct sparx5_ops *ops = sparx5->data->ops; in sparx5_to_high_dev()
59 static inline u32 sparx5_to_pcs_dev(struct sparx5 *sparx5, int port) in sparx5_to_pcs_dev() argument
61 const struct sparx5_ops *ops = sparx5->data->ops; in sparx5_to_pcs_dev()
70 static inline u32 sparx5_port_dev_mapping(struct sparx5 *sparx5, int port) in sparx5_port_dev_mapping() argument
82 static inline u32 sparx5_port_dev_index(struct sparx5 *sparx5, int port) in sparx5_port_dev_index() argument
84 return sparx5->data->ops->get_port_dev_index(sparx5, port); in sparx5_port_dev_index()
87 int sparx5_port_init(struct sparx5 *sparx5,
91 int sparx5_port_config(struct sparx5 *sparx5,
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Dsparx5_police.c2 /* Microchip Sparx5 Switch driver
10 static int sparx5_policer_service_conf_set(struct sparx5 *sparx5, in sparx5_policer_service_conf_set() argument
14 const struct sparx5_ops *ops = sparx5->data->ops; in sparx5_policer_service_conf_set()
24 pup_tokens = sparx5_sdlb_pup_token_get(sparx5, g->pup_interval, rate); in sparx5_policer_service_conf_set()
26 sparx5_sdlb_pup_token_get(sparx5, g->pup_interval, g->max_rate); in sparx5_policer_service_conf_set()
30 spx5_wr(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_SET(pup_tokens), sparx5, in sparx5_policer_service_conf_set()
34 ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX, sparx5, in sparx5_policer_service_conf_set()
38 sparx5, ANA_AC_SDLB_THRES(idx, 0)); in sparx5_policer_service_conf_set()
43 int sparx5_policer_conf_set(struct sparx5 *sparx5, struct sparx5_policer *pol) in sparx5_policer_conf_set() argument
48 return sparx5_policer_service_conf_set(sparx5, pol); in sparx5_policer_conf_set()
Dsparx5_vcap_debugfs.c2 /* Microchip Sparx5 Switch driver VCAP debugFS implementation
76 static void sparx5_vcap_is0_port_keys(struct sparx5 *sparx5, in sparx5_vcap_is0_port_keys() argument
90 value = spx5_rd(sparx5, in sparx5_vcap_is0_port_keys()
119 static void sparx5_vcap_is2_port_keys(struct sparx5 *sparx5, in sparx5_vcap_is2_port_keys() argument
133 value = spx5_rd(sparx5, ANA_ACL_VCAP_S2_CFG(port->portno)); in sparx5_vcap_is2_port_keys()
141 value = spx5_rd(sparx5, in sparx5_vcap_is2_port_keys()
232 static void sparx5_vcap_is2_port_stickies(struct sparx5 *sparx5, in sparx5_vcap_is2_port_stickies() argument
243 value = spx5_rd(sparx5, ANA_ACL_SEC_LOOKUP_STICKY(lookup)); in sparx5_vcap_is2_port_stickies()
282 spx5_wr(value, sparx5, ANA_ACL_SEC_LOOKUP_STICKY(lookup)); in sparx5_vcap_is2_port_stickies()
287 static void sparx5_vcap_es0_port_keys(struct sparx5 *sparx5, in sparx5_vcap_es0_port_keys() argument
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Dsparx5_tc_matchall.c53 struct sparx5 *sparx5; in sparx5_tc_matchall_replace() local
73 sparx5 = port->sparx5; in sparx5_tc_matchall_replace()
103 err = vcap_enable_lookups(sparx5->vcap_ctrl, ndev, in sparx5_tc_matchall_replace()
133 list_add_tail(&mall_entry->list, &sparx5->mall_entries); in sparx5_tc_matchall_replace()
143 struct sparx5 *sparx5 = port->sparx5; in sparx5_tc_matchall_destroy() local
147 entry = sparx5_tc_matchall_entry_find(&sparx5->mall_entries, in sparx5_tc_matchall_destroy()
155 err = vcap_enable_lookups(sparx5->vcap_ctrl, ndev, in sparx5_tc_matchall_destroy()
172 struct sparx5 *sparx5 = port->sparx5; in sparx5_tc_matchall_stats() local
175 entry = sparx5_tc_matchall_entry_find(&sparx5->mall_entries, in sparx5_tc_matchall_stats()
/linux-6.14.4/drivers/net/ethernet/microchip/vcap/
Dvcap_ag_api.h28 VCAP_KFS_ARP, /* sparx5 is2 X6, sparx5 es2 X6, lan966x is2 X2 */
31 VCAP_KFS_ETAG, /* sparx5 is0 X2 */
32 VCAP_KFS_IP4_OTHER, /* sparx5 is2 X6, sparx5 es2 X6, lan966x is2 X2 */
33 VCAP_KFS_IP4_TCP_UDP, /* sparx5 is2 X6, sparx5 es2 X6, lan966x is2 X2 */
34 VCAP_KFS_IP4_VID, /* sparx5 es2 X3 */
36 VCAP_KFS_IP6_STD, /* sparx5 is2 X6, sparx5 es2 X6, lan966x is2 X2 */
38 VCAP_KFS_IP6_VID, /* sparx5 es2 X6 */
39 VCAP_KFS_IP_7TUPLE, /* sparx5 is2 X12, sparx5 es2 X12 */
40 VCAP_KFS_ISDX, /* sparx5 es0 X1 */
41 VCAP_KFS_LL_FULL, /* sparx5 is0 X6 */
[all …]
/linux-6.14.4/drivers/net/ethernet/microchip/sparx5/lan969x/
Dlan969x_fdma.c15 #define FDMA_PRIV(fdma) ((struct sparx5 *)((fdma)->priv))
53 static void lan969x_fdma_tx_clear_buf(struct sparx5 *sparx5, int weight) in lan969x_fdma_tx_clear_buf() argument
55 struct fdma *fdma = &sparx5->tx.fdma; in lan969x_fdma_tx_clear_buf()
60 spin_lock_irqsave(&sparx5->tx_lock, flags); in lan969x_fdma_tx_clear_buf()
63 db = &sparx5->tx.dbs[i]; in lan969x_fdma_tx_clear_buf()
73 sparx5->tx.packets++; in lan969x_fdma_tx_clear_buf()
75 dma_unmap_single(sparx5->dev, in lan969x_fdma_tx_clear_buf()
86 spin_unlock_irqrestore(&sparx5->tx_lock, flags); in lan969x_fdma_tx_clear_buf()
100 static struct sk_buff *lan969x_fdma_rx_get_frame(struct sparx5 *sparx5, in lan969x_fdma_rx_get_frame() argument
103 const struct sparx5_consts *consts = sparx5->data->consts; in lan969x_fdma_rx_get_frame()
[all …]
Dlan969x.h10 #include "../sparx5/sparx5_main.h"
11 #include "../sparx5/sparx5_regs.h"
12 #include "../sparx5/sparx5_vcap_impl.h"
68 int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi,
76 int lan969x_fdma_init(struct sparx5 *sparx5);
77 int lan969x_fdma_deinit(struct sparx5 *sparx5);
79 int lan969x_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb,
/linux-6.14.4/Documentation/devicetree/bindings/arm/
Dmicrochip,sparx5.yaml4 $id: http://devicetree.org/schemas/arm/microchip,sparx5.yaml#
7 title: Microchip Sparx5 Boards
13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
27 - description: The Sparx5 pcb125 board is a modular board,
31 - const: microchip,sparx5-pcb125
32 - const: microchip,sparx5
34 - description: The Sparx5 pcb134 is a pizzabox form factor
38 - const: microchip,sparx5-pcb134
39 - const: microchip,sparx5
41 - description: The Sparx5 pcb135 is a pizzabox form factor
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