| /XiangShan/ |
| H A D | README.md | diff 05f23f575dc9b9d5ecb9f7884862bbe593024bf4 Wed May 12 13:13:07 CEST 2021 William Wang <[email protected]> Configs: update MinimalConfig for FPGA (#809)
* Configs: add MinimalFPGAConfig
* TODO: change cache parameters
* Chore: add parameter print
* README: add simulation usage
Currently, XiangShan does not support NOOP FPGA. FPGA related
instructions are removed
* Configs: limit frontend width in MinimalConfig
* MinimalConfig: limit L1/L2 cache size
* MinimalConfig: limit ptw size, disable L2
* MinimalConfig: limit L3 size
* Sbuffer: force trigger write if sbuffer fulls
|
| H A D | Makefile | diff 05f23f575dc9b9d5ecb9f7884862bbe593024bf4 Wed May 12 13:13:07 CEST 2021 William Wang <[email protected]> Configs: update MinimalConfig for FPGA (#809)
* Configs: add MinimalFPGAConfig
* TODO: change cache parameters
* Chore: add parameter print
* README: add simulation usage
Currently, XiangShan does not support NOOP FPGA. FPGA related
instructions are removed
* Configs: limit frontend width in MinimalConfig
* MinimalConfig: limit L1/L2 cache size
* MinimalConfig: limit ptw size, disable L2
* MinimalConfig: limit L3 size
* Sbuffer: force trigger write if sbuffer fulls
|
| /XiangShan/src/main/scala/xiangshan/backend/regfile/ |
| H A D | Regfile.scala | diff 05f23f575dc9b9d5ecb9f7884862bbe593024bf4 Wed May 12 13:13:07 CEST 2021 William Wang <[email protected]> Configs: update MinimalConfig for FPGA (#809)
* Configs: add MinimalFPGAConfig
* TODO: change cache parameters
* Chore: add parameter print
* README: add simulation usage
Currently, XiangShan does not support NOOP FPGA. FPGA related
instructions are removed
* Configs: limit frontend width in MinimalConfig
* MinimalConfig: limit L1/L2 cache size
* MinimalConfig: limit ptw size, disable L2
* MinimalConfig: limit L3 size
* Sbuffer: force trigger write if sbuffer fulls
|
| /XiangShan/src/main/scala/system/ |
| H A D | SoC.scala | diff 05f23f575dc9b9d5ecb9f7884862bbe593024bf4 Wed May 12 13:13:07 CEST 2021 William Wang <[email protected]> Configs: update MinimalConfig for FPGA (#809)
* Configs: add MinimalFPGAConfig
* TODO: change cache parameters
* Chore: add parameter print
* README: add simulation usage
Currently, XiangShan does not support NOOP FPGA. FPGA related
instructions are removed
* Configs: limit frontend width in MinimalConfig
* MinimalConfig: limit L1/L2 cache size
* MinimalConfig: limit ptw size, disable L2
* MinimalConfig: limit L3 size
* Sbuffer: force trigger write if sbuffer fulls
|
| /XiangShan/src/main/scala/top/ |
| H A D | Configs.scala | diff 05f23f575dc9b9d5ecb9f7884862bbe593024bf4 Wed May 12 13:13:07 CEST 2021 William Wang <[email protected]> Configs: update MinimalConfig for FPGA (#809)
* Configs: add MinimalFPGAConfig
* TODO: change cache parameters
* Chore: add parameter print
* README: add simulation usage
Currently, XiangShan does not support NOOP FPGA. FPGA related
instructions are removed
* Configs: limit frontend width in MinimalConfig
* MinimalConfig: limit L1/L2 cache size
* MinimalConfig: limit ptw size, disable L2
* MinimalConfig: limit L3 size
* Sbuffer: force trigger write if sbuffer fulls
|
| /XiangShan/src/main/scala/xiangshan/backend/fu/ |
| H A D | CSR.scala | diff 05f23f575dc9b9d5ecb9f7884862bbe593024bf4 Wed May 12 13:13:07 CEST 2021 William Wang <[email protected]> Configs: update MinimalConfig for FPGA (#809)
* Configs: add MinimalFPGAConfig
* TODO: change cache parameters
* Chore: add parameter print
* README: add simulation usage
Currently, XiangShan does not support NOOP FPGA. FPGA related
instructions are removed
* Configs: limit frontend width in MinimalConfig
* MinimalConfig: limit L1/L2 cache size
* MinimalConfig: limit ptw size, disable L2
* MinimalConfig: limit L3 size
* Sbuffer: force trigger write if sbuffer fulls
|
| /XiangShan/src/main/scala/xiangshan/mem/lsqueue/ |
| H A D | LoadQueue.scala | diff 05f23f575dc9b9d5ecb9f7884862bbe593024bf4 Wed May 12 13:13:07 CEST 2021 William Wang <[email protected]> Configs: update MinimalConfig for FPGA (#809)
* Configs: add MinimalFPGAConfig
* TODO: change cache parameters
* Chore: add parameter print
* README: add simulation usage
Currently, XiangShan does not support NOOP FPGA. FPGA related
instructions are removed
* Configs: limit frontend width in MinimalConfig
* MinimalConfig: limit L1/L2 cache size
* MinimalConfig: limit ptw size, disable L2
* MinimalConfig: limit L3 size
* Sbuffer: force trigger write if sbuffer fulls
|
| H A D | StoreQueue.scala | diff 05f23f575dc9b9d5ecb9f7884862bbe593024bf4 Wed May 12 13:13:07 CEST 2021 William Wang <[email protected]> Configs: update MinimalConfig for FPGA (#809)
* Configs: add MinimalFPGAConfig
* TODO: change cache parameters
* Chore: add parameter print
* README: add simulation usage
Currently, XiangShan does not support NOOP FPGA. FPGA related
instructions are removed
* Configs: limit frontend width in MinimalConfig
* MinimalConfig: limit L1/L2 cache size
* MinimalConfig: limit ptw size, disable L2
* MinimalConfig: limit L3 size
* Sbuffer: force trigger write if sbuffer fulls
|
| /XiangShan/src/main/scala/xiangshan/ |
| H A D | Parameters.scala | diff 05f23f575dc9b9d5ecb9f7884862bbe593024bf4 Wed May 12 13:13:07 CEST 2021 William Wang <[email protected]> Configs: update MinimalConfig for FPGA (#809)
* Configs: add MinimalFPGAConfig
* TODO: change cache parameters
* Chore: add parameter print
* README: add simulation usage
Currently, XiangShan does not support NOOP FPGA. FPGA related
instructions are removed
* Configs: limit frontend width in MinimalConfig
* MinimalConfig: limit L1/L2 cache size
* MinimalConfig: limit ptw size, disable L2
* MinimalConfig: limit L3 size
* Sbuffer: force trigger write if sbuffer fulls
|