Searched hist:"51981 c77c37dd3d7ecd4849a0cfb6b431a922958" (Results 1 – 8 of 8) sorted by relevance
| /XiangShan/ |
| H A D | Makefile.test | 51981c77c37dd3d7ecd4849a0cfb6b431a922958 Tue Feb 14 02:52:51 CET 2023 bugGenerator <[email protected]> test: add example of chiseltest's unit-test and generating verilog for xs' module (#1890)
* test: add example to genenrate verilog for a small module
Just use Parameters from DefaultConfig(& Argparser) like XSTop/SimTop
* test: add DecodeUnitTest as an example for xs' chiseltest
* ctrlblock: <> usage has changed, unidirection should use :=
* bump huancun
* makefile: mv new makefile cmd into Makefile.test
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| H A D | build.sc | diff 51981c77c37dd3d7ecd4849a0cfb6b431a922958 Tue Feb 14 02:52:51 CET 2023 bugGenerator <[email protected]> test: add example of chiseltest's unit-test and generating verilog for xs' module (#1890)
* test: add example to genenrate verilog for a small module
Just use Parameters from DefaultConfig(& Argparser) like XSTop/SimTop
* test: add DecodeUnitTest as an example for xs' chiseltest
* ctrlblock: <> usage has changed, unidirection should use :=
* bump huancun
* makefile: mv new makefile cmd into Makefile.test
|
| H A D | Makefile | diff 51981c77c37dd3d7ecd4849a0cfb6b431a922958 Tue Feb 14 02:52:51 CET 2023 bugGenerator <[email protected]> test: add example of chiseltest's unit-test and generating verilog for xs' module (#1890)
* test: add example to genenrate verilog for a small module
Just use Parameters from DefaultConfig(& Argparser) like XSTop/SimTop
* test: add DecodeUnitTest as an example for xs' chiseltest
* ctrlblock: <> usage has changed, unidirection should use :=
* bump huancun
* makefile: mv new makefile cmd into Makefile.test
|
| /XiangShan/src/test/scala/fu/ |
| H A D | IntDiv.scala | diff 51981c77c37dd3d7ecd4849a0cfb6b431a922958 Tue Feb 14 02:52:51 CET 2023 bugGenerator <[email protected]> test: add example of chiseltest's unit-test and generating verilog for xs' module (#1890)
* test: add example to genenrate verilog for a small module
Just use Parameters from DefaultConfig(& Argparser) like XSTop/SimTop
* test: add DecodeUnitTest as an example for xs' chiseltest
* ctrlblock: <> usage has changed, unidirection should use :=
* bump huancun
* makefile: mv new makefile cmd into Makefile.test
|
| /XiangShan/src/test/scala/xiangshan/ |
| H A D | XSTester.scala | 51981c77c37dd3d7ecd4849a0cfb6b431a922958 Tue Feb 14 02:52:51 CET 2023 bugGenerator <[email protected]> test: add example of chiseltest's unit-test and generating verilog for xs' module (#1890)
* test: add example to genenrate verilog for a small module
Just use Parameters from DefaultConfig(& Argparser) like XSTop/SimTop
* test: add DecodeUnitTest as an example for xs' chiseltest
* ctrlblock: <> usage has changed, unidirection should use :=
* bump huancun
* makefile: mv new makefile cmd into Makefile.test
|
| H A D | DecodeTest.scala | 51981c77c37dd3d7ecd4849a0cfb6b431a922958 Tue Feb 14 02:52:51 CET 2023 bugGenerator <[email protected]> test: add example of chiseltest's unit-test and generating verilog for xs' module (#1890)
* test: add example to genenrate verilog for a small module
Just use Parameters from DefaultConfig(& Argparser) like XSTop/SimTop
* test: add DecodeUnitTest as an example for xs' chiseltest
* ctrlblock: <> usage has changed, unidirection should use :=
* bump huancun
* makefile: mv new makefile cmd into Makefile.test
|
| /XiangShan/src/main/scala/xiangshan/frontend/ |
| H A D | NewFtq.scala | diff 51981c77c37dd3d7ecd4849a0cfb6b431a922958 Tue Feb 14 02:52:51 CET 2023 bugGenerator <[email protected]> test: add example of chiseltest's unit-test and generating verilog for xs' module (#1890)
* test: add example to genenrate verilog for a small module
Just use Parameters from DefaultConfig(& Argparser) like XSTop/SimTop
* test: add DecodeUnitTest as an example for xs' chiseltest
* ctrlblock: <> usage has changed, unidirection should use :=
* bump huancun
* makefile: mv new makefile cmd into Makefile.test
|
| /XiangShan/src/main/scala/xiangshan/backend/ |
| H A D | CtrlBlock.scala | diff 51981c77c37dd3d7ecd4849a0cfb6b431a922958 Tue Feb 14 02:52:51 CET 2023 bugGenerator <[email protected]> test: add example of chiseltest's unit-test and generating verilog for xs' module (#1890)
* test: add example to genenrate verilog for a small module
Just use Parameters from DefaultConfig(& Argparser) like XSTop/SimTop
* test: add DecodeUnitTest as an example for xs' chiseltest
* ctrlblock: <> usage has changed, unidirection should use :=
* bump huancun
* makefile: mv new makefile cmd into Makefile.test
|