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Searched defs:target (Results 1 – 12 of 12) sorted by relevance

/XiangShan/src/main/scala/xiangshan/backend/issue/
H A DBypassNetwork.scala35 val target = Vec(numWays, Output(UInt(dataBits.W))) constant
46 val target = Mux(bypassVec.asUInt.orR, ParallelMux(bypassValid, bypassData), baseData) constant
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/
H A DBranchUnit.scala18 val target = Output(UInt(XLEN.W)) constant
/XiangShan/src/main/scala/xiangshan/backend/fu/
H A DJump.scala52 …val target = Mux(JumpOpType.jumpOpisJalr(func), src1 + offset, pc + offset) // NOTE: src1 is (pc/r… constant
H A DFuncUnit.scala32 val target = UInt(VAddrData().dataWidth.W) constant
/XiangShan/src/main/scala/xiangshan/frontend/
H A DFrontendBundle.scala100 val target = UInt(VAddrBits.W) constant
517 def target(pc: UInt): UInt method
606 def target(pc: UInt): UInt = method
691 def target(pc: UInt) = VecInit(full_pred.map(_.target(pc))) method
H A DNewFtq.scala41 val target = UInt(39.W) constant
182 val target = UInt(VAddrBits.W) constant
257 val target = Input(UInt(VAddrBits.W)) constant
1559 val target = commit_target constant
H A DFTB.scala95 val target = constant
H A DBPU.scala590 val target = Vec(numDup, UInt(VAddrBits.W)) constant
H A DIFU.scala103 val target = UInt(VAddrBits.W) constant
/XiangShan/src/main/scala/xiangshan/backend/rename/
H A DRename.scala544 val target = io.in(i).bits.lsrc constant
/XiangShan/src/main/scala/xiangshan/
H A DBundle.scala93 val target = if (!env.FPGAPlatform) UInt(VAddrBits.W) else UInt(0.W) constant
119 val target = UInt(VAddrBits.W) constant
/XiangShan/src/main/scala/xiangshan/backend/
H A DBundles.scala633 val target = UInt(VAddrData().dataWidth.W) constant