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f7af4c74 |
| 17-Nov-2023 |
chengguanghui <[email protected]> |
Debug Module: cherry-pick debug module from nanhu
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dbc1c7fc |
| 15-Nov-2023 |
zhanglinjuan <[email protected]> |
VldMergeUnit: use vdIdx inside a field to generate mask
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97b279b9 |
| 20-Nov-2023 |
Xuan Hu <[email protected]> |
fix rebase errors
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92c6b7ed |
| 08-Nov-2023 |
zhanglinjuan <[email protected]> |
Mgu: use sew as element width instead of eew for indexed loads/stores
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52c49ce8 |
| 05-Nov-2023 |
Xuan Hu <[email protected]> |
backend,param: merge vldu and vstu into one exu
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887f9c3d |
| 04-Nov-2023 |
zhanglinjuan <[email protected]> |
Backend: add uopIdx comparing logic in deqResp for vector mem iq
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7ca7ad94 |
| 01-Nov-2023 |
zhanglinjuan <[email protected]> |
UopQueue: pass on mask and vdIdx to Backend
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98d3cb16 |
| 31-Oct-2023 |
Xuan Hu <[email protected]> |
backend: fix VldMergeUnit
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e703da02 |
| 08-Oct-2023 |
zhanglyGit <[email protected]> |
Backend: WBDataPath and ROB support vlsu(vld res merge and exceptionGen)
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2d270511 |
| 28-Sep-2023 |
sinsanction <[email protected]> |
IssueQueue: add vector load/store IssueQueue
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f19cc441 |
| 26-Oct-2023 |
zhanglinjuan <[email protected]> |
UopQueue: use decode result instead of decoding repeatedly
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20a5248f |
| 19-Oct-2023 |
zhanglinjuan <[email protected]> |
Add VLSU
* miscs: optimize code style
* vector: add VLSU param system and redefine vector lq io
* VLUopQueue: add flow split and address generation logic
* VLUopQueue: add flow issue and writebac
Add VLSU
* miscs: optimize code style
* vector: add VLSU param system and redefine vector lq io
* VLUopQueue: add flow split and address generation logic
* VLUopQueue: add flow issue and writeback logic
* VLUopQueue: set vstart for elements with exception
* VLUopQueue: handle unit-stride fof loads
* VLUopQueue: implement vector masking according to vm
* vector: rewrite vector store io
* VlFlowQueue: add enqueue and dequeue logic
* VLFlowQueue: fix some coding problem
* VlFlowQueue: add issue, replay and result logic
* VLFlowQueue: add redirect logic
* Rob: fix compilation error
* vector: remove stale codes
* vector: add VSUopQueue and fix bugs for vector load
* backbone: add vector load/store execution paths
* VSFlowQueue: Basic function
* VLUopQueue: add redirect logic for load-load violation
* VSFlowQueue: fix some compile problems
* VSUopQueue: add signal to indicate whether a flow is the last one
* VSFlowQueue: inform scala sq when vector store finished
* StoreQueue: maintain sequential retirement between scalar & vector stores
* LoadQueueRAW: handle violation between vector stores & scalar loads
* LDU: add vector store to scalar load forwarding
* XSCore: fix writeback width of MemBlock
* vector: fix load/store whole register and masked unit-stride load/store emul, evl, flownum (#2383)
* VSFlowQueue: Support STLF
* VLFlowQueue: fix compile bug
* VSFlowQueue: fix compile problem
---------
Co-authored-by: xuzefan <[email protected]> Co-authored-by: good-circle <[email protected]> Co-authored-by: weidingliu <[email protected]>
show more ...
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5b35049a |
| 09-Nov-2023 |
Haojin Tang <[email protected]> |
IssueQueue: prevent store from dequeuing after issue success
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04c99eca |
| 05-Nov-2023 |
Xuan Hu <[email protected]> |
backend: fix load cancel bundle
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8a66c02c |
| 03-Nov-2023 |
Xuan Hu <[email protected]> |
dispatch2iq: fix dispatch error
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c838dea1 |
| 02-Nov-2023 |
Xuan Hu <[email protected]> |
backend: fix compile errors
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546a0d46 |
| 02-Nov-2023 |
Xuan Hu <[email protected]> |
backend: fix load issue ports sort
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14525be7 |
| 02-Nov-2023 |
Xuan Hu <[email protected]> |
backend: fix load writeback sort
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ecfc6f16 |
| 31-Oct-2023 |
Xuan Hu <[email protected]> |
backend: refactor Dispatch2IqMemImp
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670870b3 |
| 25-Oct-2023 |
Xuan Hu <[email protected]> |
backend: support hybrid unit
* filter not fake unit when generate bundles * add fake exu unit * hybrid unit use one load writeback port and one store writeback port
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3ad3585e |
| 25-Oct-2023 |
Xuan Hu <[email protected]> |
backend,mem: split hybrid units writeback bundle
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6810d1e8 |
| 25-Oct-2023 |
sfencevma <[email protected]> |
fix params
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f9f1abd7 |
| 23-Oct-2023 |
Xuan Hu <[email protected]> |
backend: support HybridUnit at Dispatch Stage
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94d19d83 |
| 23-Oct-2023 |
sfencevma <[email protected]> |
add std and hybrid writeback ports to Backend
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536d1e29 |
| 23-Oct-2023 |
sfencevma <[email protected]> |
add writeback port to Backend
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