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db3923fe07-Mar-2025 Guanghui Cheng <[email protected]>

fix(Trigger): fix comparison between consecutive pc and tdada2 (#4346)


/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/perf.yml
/XiangShan/Makefile
/XiangShan/README.md
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/huancun
/XiangShan/openLLC
/XiangShan/readme.zh-cn.md
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/top-down/configs.py
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/resources/config/Default.yml
/XiangShan/src/main/scala/device/AXI4Memory.scala
/XiangShan/src/main/scala/device/MemEncrypt.scala
/XiangShan/src/main/scala/device/MemEncryptUtil.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/top/YamlParser.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/PMParameters.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRCustom.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/DretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MNretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/SretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSROoORead.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PFEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SstcInterruptGen.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/Trigger.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/CacheConstants.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/BitmapCheck.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/Bundles.scala
/XiangShan/src/main/scala/xiangshan/mem/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchInterface.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StreamPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/PrefetcherMonitor.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
scala/xiangshan/frontend/FrontTrigger.scala
/XiangShan/utility
/XiangShan/yunsuan
2095784610-Jan-2025 Zihao Yu <[email protected]>

fix(device, DebugMoudle): do not use clock with Bool type (#4152)

* gsim can not handle such clocks


/XiangShan/.github/CODEOWNERS
/XiangShan/.github/workflows/perf.yml
/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/openLLC
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/device/RocketDebugWrapper.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRCustom.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PMPEntryModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheCtrlUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
scala/top/SimTop.scala
/XiangShan/utility
12c5a99813-Dec-2024 klin02 <[email protected]>

submodule(utility), transforms: collect XSLogs to SimTop.LogPerfEndpoint

XSLog depends on LogPerfCtrl declared at Top Module. Previous we
annotate such signal as dontTouch, and accessed through Hier

submodule(utility), transforms: collect XSLogs to SimTop.LogPerfEndpoint

XSLog depends on LogPerfCtrl declared at Top Module. Previous we
annotate such signal as dontTouch, and accessed through Hierarchical
name like SimTop.xx by dummy LogPerfHelper.

However, as XSLog is called in many spaces in DUT, which are not
visible to each other, especailly some in WhenContext. XS will generate
thousands of LogPerfHelper to get same LogPerfCtrl. Too many module
instantiations greately slow down compilation speed, especailly in
Palladium (more than 5 times slower than same DUT without Log).

This change collect all XSLog to SimTop.LogPerfEndpoint, with
LogPerfCtrl directly passed by IO. Some tips as follows:

1. Not call XSLog inside whenContext. To collect XSLogs, we should
access Cond and Data from other module, but data in WhenContext is
not accessible even through tap. Use XSLog(cond, pable) instead of
when(cond) {XSLog(pable)}. We also add chisel Internal API currentWhen
to check that.

2. Generate Hierarchical Module path through FIRRTL transforms.
Sometimes we want to append module path for better debugging.
XSCompatibility add a hacky way to use Chisel internal API to get
tag of current Module. Then we will replace these tag with
path during ChiselStage. Note path can only be acessed after circuit
elaboration.

3. Register and invoke caller of XSPerf and related object. As XSPerf
depends on LogPerfCtrl such as dump. We should deferred apply() until
collect. So we regirster collect() method when firstly apply XSLog,
then XSLog will automatically call XSPerf.collect() method during
collection. Note deferred apply is called in another module, so original
module tag should be recorded for path generation.

4. Concat XSLogs with same condition. Too many fwrites in same module
will cause UPOPTTHREADS warning with 16-threads Verilator. Consider
many XSLogs have same condition (especailly XSPerfs), we reuse same
condition and concat their printables to reduce fwrites. Note we also
limit size of concatation to 1000 to avoid segmentation fault caused
by too long printf.

show more ...


/XiangShan/src/main/scala/device/AXI4SlaveModule.scala
/XiangShan/src/main/scala/device/TLTimer.scala
/XiangShan/src/main/scala/utils/DebugIdentityNode.scala
/XiangShan/src/main/scala/utils/TLDump.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FpPipedFuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/BranchUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Snapshot.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobDeqPtrWrapper.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/Interface.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/Trace.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/WaitTable.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/transforms/PrintModuleName.scala
scala/top/SimTop.scala
/XiangShan/utility
0a7d1d5c22-Nov-2024 xiaofeibao <[email protected]>

feat(backend): NewDispatch


/XiangShan/.github/filters.yaml
/XiangShan/.github/workflows/format.yml
/XiangShan/coupledL2
/XiangShan/ready-to-run
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/device/AXI4IntrGenerator.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2IqFpImp.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheTagTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/CompressUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/Interface.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/Trace.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/TraceBuffer.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/CtrlUnit.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/package.scala
725e8ddc19-Sep-2024 chengguanghui <[email protected]>

feat(trace): add TraceCoreInterface in top.


/XiangShan/.github/filters.yaml
/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/format.yml
/XiangShan/.github/workflows/perf.yml
/XiangShan/.gitignore
/XiangShan/.mill-version
/XiangShan/.scalafmt.conf
/XiangShan/Makefile
/XiangShan/README.md
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/images/xs-arch-kunminghu.svg
/XiangShan/openLLC
/XiangShan/readme.zh-cn.md
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/device/IMSIC.scala
/XiangShan/src/main/scala/device/imsic_axi_top.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDevice.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/top/XiangShanStage.scala
/XiangShan/src/main/scala/utils/AXI4Lite.scala
/XiangShan/src/main/scala/utils/SeqUtils.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSDts.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/README.md
/XiangShan/src/main/scala/xiangshan/backend/VecExcpDataMergeModule.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/DretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MNretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/SretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryDEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CommitIDModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PMPEntryModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheTagModule.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/CompressUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/ExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/Interface.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/Trace.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/TraceBuffer.scala
/XiangShan/src/main/scala/xiangshan/cache/CacheConstants.scala
/XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AMOALU.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Bim.scala
/XiangShan/src/main/scala/xiangshan/frontend/Composer.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/RAS.scala
/XiangShan/src/main/scala/xiangshan/frontend/README.md
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/FIFO.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/WaitTable.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/FDP.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
scala/top/SimTop.scala
/XiangShan/utility
/XiangShan/yunsuan
fab8b27416-Oct-2024 Haoyuan Feng <[email protected]>

fix(SimTop): Set sim memory size same as PMA (#3750)

bbe4506d15-Oct-2024 Tang Haojin <[email protected]>

fix(MMIO): use fine-grained on-chip MMIO ranges (#3730)

Previously, on-chip devices use a continuous memory range, which
contains many memory holes not actually used. If we access these holes,
the

fix(MMIO): use fine-grained on-chip MMIO ranges (#3730)

Previously, on-chip devices use a continuous memory range, which
contains many memory holes not actually used. If we access these holes,
the core will hang. This commit use fine-grained on-chip MMIO ranges so
that memory accessing of these holes will be routed out of core and
handled by other mechanisms.

show more ...

8bc9063105-Oct-2024 Zehao Liu <[email protected]>

fix(Smrnmi): expand NMI interrupt to two types and route the nmi signals to XSTOP (#3691)


/XiangShan/.github/workflows/emu.yml
/XiangShan/Makefile
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/ready-to-run
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/device/imsic_axi_top.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/PMParameters.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSDts.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/VecExcpDataMergeModule.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/DretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MNretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/SretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryDEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMNEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRFields.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/ExceptionBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapInstMod.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/ExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/storepipe/StorePipe.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchInterface.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VfofBuffer.scala
/XiangShan/src/main/scala/xiangshan/package.scala
scala/top/SimTop.scala
/XiangShan/utility
233f2ad020-Sep-2024 zhanglinjuan <[email protected]>

feat: implement a new version of reset tree (#3546)

This commit uses `LazyRawModuleImp` to implement L2Top, MemBlock,
Backend and frontend so that when `--reset-gen` option is enabled, reset
input

feat: implement a new version of reset tree (#3546)

This commit uses `LazyRawModuleImp` to implement L2Top, MemBlock,
Backend and frontend so that when `--reset-gen` option is enabled, reset
input of these modules will go through `ResetGen` and then drives the
reset of the registers inside the module.

<img
src="https://github.com/user-attachments/assets/1f544afe-4644-4604-ba6f-d14d31909f78"
width="50%">

---------
Co-authored-by: chengguanghui <[email protected]>

show more ...


/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/perf.yml
/XiangShan/Makefile
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/parser.py
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/resources/aia
/XiangShan/src/main/scala/device/IMSICAsync.scala
/XiangShan/src/main/scala/device/RocketDebugWrapper.scala
/XiangShan/src/main/scala/device/imsic_axi_top.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDevice.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/PMParameters.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSDts.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchInterface.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
scala/xiangshan/backend/dispatch/Dispatch2IqMain.scala
/XiangShan/utility
d880df4531-Aug-2024 zhanglinjuan <[email protected]>

SimMMIO: add AXI4Error to handle void address space


/XiangShan/.github/filters.yaml
/XiangShan/.github/workflows/check_verilog.py
/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/perf.yml
/XiangShan/Makefile
/XiangShan/README.md
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/huancun
/XiangShan/openLLC
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/generate_all.sh
/XiangShan/scripts/parser.py
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/resources/aia
/XiangShan/src/main/scala/device/AXI4Flash.scala
/XiangShan/src/main/scala/device/IMSIC.scala
/XiangShan/src/main/scala/device/IMSICAsync.scala
/XiangShan/src/main/scala/device/imsic_axi_top.scala
/XiangShan/src/main/scala/device/standalone/StandAloneCLINT.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDevice.scala
/XiangShan/src/main/scala/device/standalone/StandAlonePLIC.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/utils/NamedUInt.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/DbEntry.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/PipeGroupConnect.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataSource.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/Og2ForVector.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/Instructions.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRCustom.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/DretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MNretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/SretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryDEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMNEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapInstMod.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapTvalMod.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FliTable.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntFPToVec.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/BranchUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/AgeDetector.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/RegCache.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheAgeTimer.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheDataModule.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheTagModule.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheTagTable.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/CompressUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/ExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/Interface.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/AsynchronousMetaArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/cache/wpu/VictimList.scala
/XiangShan/src/main/scala/xiangshan/cache/wpu/WPUWrapper.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/FreeList.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchInterface.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StreamPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/PrefetcherMonitor.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
scala/top/SimMMIO.scala
/XiangShan/utility
/XiangShan/yunsuan
e3da8bad22-Jul-2024 Tang Haojin <[email protected]>

build: purge chisel 3 and add deprecation check (#3250)


/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/nightly.yml
/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/ready-to-run
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/resources/aia
/XiangShan/src/main/scala/device/IMSIC.scala
/XiangShan/src/main/scala/device/imsic_axi_top.scala
/XiangShan/src/main/scala/device/standalone/StandAloneCLINT.scala
/XiangShan/src/main/scala/device/standalone/standalone_device.mk
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Generator.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/top/XiangShanStage.scala
/XiangShan/src/main/scala/utils/DebugMem.scala
/XiangShan/src/main/scala/utils/MapUtils.scala
/XiangShan/src/main/scala/utils/SeqUtils.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRCustom.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/DretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryDEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRFields.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPMP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/ExceptionBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PMPEntryModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SstcInterruptGen.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/StateEnBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/Trigger.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala
/XiangShan/src/main/scala/xiangshan/backend/implicitCast.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/FIFO.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StreamPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/main/scala/xiangshan/transforms/Helpers.scala
/XiangShan/src/main/scala/xiangshan/transforms/NestedPrefixModulesAnnotation.scala
/XiangShan/src/main/scala/xiangshan/transforms/PrintControl.scala
/XiangShan/src/main/scala/xiangshan/transforms/PrintModuleName.scala
scala/fu/IntDiv.scala
scala/xiangshan/DecodeTest.scala
scala/xiangshan/XSTester.scala
615948e405-May-2024 Xuan Hu <[email protected]>

Backend: remove useless firtool args in BackendMain


/XiangShan/build.sc
/XiangShan/macros/src/main/scala/CSRMacros.scala
/XiangShan/src/main/resources/vsrc/cmip_dff_sync.sv
/XiangShan/src/main/resources/vsrc/imsic/imsic_csr_gate.v
/XiangShan/src/main/resources/vsrc/imsic/imsic_csr_reg.v
/XiangShan/src/main/resources/vsrc/imsic/imsic_csr_top.v
/XiangShan/src/main/scala/device/IMSIC.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/PseudoInstruction.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAnnotation.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRCustom.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/DretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/SretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRFields.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRNamedConstant.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/ExceptionBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/package.scala
scala/xiangshan/backend/BackendMain.scala
ae0295f416-Jul-2024 Tang Haojin <[email protected]>

chore: bump chisel 6.5.0 (#3210)


/XiangShan/.github/workflows/emu.yml
/XiangShan/.gitmodules
/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/huancun
/XiangShan/openLLC
/XiangShan/scripts/xiangshan.py
/XiangShan/src/chisel/main/scala/xiangshan/transforms/PrintModuleName.scala
/XiangShan/src/chisel3/main/scala/xiangshan/transforms/PrintModuleName.scala
/XiangShan/src/main/resources/aia
/XiangShan/src/main/scala/device/AXI4Memory.scala
/XiangShan/src/main/scala/device/AXI4Plic.scala
/XiangShan/src/main/scala/device/TLTimer.scala
/XiangShan/src/main/scala/device/imsic_axi_top.scala
/XiangShan/src/main/scala/device/standalone/StandAloneCLINT.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDevice.scala
/XiangShan/src/main/scala/device/standalone/StandAlonePLIC.scala
/XiangShan/src/main/scala/device/standalone/standalone_device.mk
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/BusPerfMonitor.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/utils/AXI4Lite.scala
/XiangShan/src/main/scala/utils/DebugIdentityNode.scala
/XiangShan/src/main/scala/utils/PerfCounterUtils.scala
/XiangShan/src/main/scala/utils/TLDump.scala
/XiangShan/src/main/scala/utils/Trigger.scala
/XiangShan/src/main/scala/utils/VerilogAXI4LiteRecord.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/PipeGroupConnect.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFReadArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2IqFpImp.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Bku.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Vsetu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/ByteMaskTailGen.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIDiv.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Snapshot.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobDeqPtrWrapper.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/storepipe/StorePipe.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/wpu/WPU.scala
/XiangShan/src/main/scala/xiangshan/cache/wpu/WPUWrapper.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
scala/top/SimTop.scala
/XiangShan/utility
/XiangShan/yunsuan
1bf9a05a02-Jul-2024 zhanglinjuan <[email protected]>

SoC, Top: use Option for SoC widgets concerning L3

78a8cd2530-Jun-2024 zhanglinjuan <[email protected]>

SoC: an initial version of DummyLLC

2993c5ec27-Jun-2024 Haojin Tang <[email protected]>

Top: use VerilogAXI4Record instead of `sed` to handle amba signal names

195ef4a528-Jun-2024 Tang Haojin <[email protected]>

build: bump chisel 3.6.1, scala 2.13.14, mill 0.11.8, etc. (#3118)


/XiangShan/.github/CODEOWNERS
/XiangShan/.github/ISSUE_TEMPLATE/1-bug_report.yml
/XiangShan/.github/ISSUE_TEMPLATE/2-feature_request.yaml
/XiangShan/.github/ISSUE_TEMPLATE/3-problem.yaml
/XiangShan/.github/ISSUE_TEMPLATE/4-other_question.yml
/XiangShan/.github/filters.yaml
/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/nightly.yml
/XiangShan/.mill-version
/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/PipeGroupConnect.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataSource.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/Og2ForVector.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFReadArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFWBConflictChecker.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RdConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiterParams.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbFuBusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2IqFpImp.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Vsetu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntFPToVec.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/DivUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/MulUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIDiv.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/MultiWakeupQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/PregParams.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/ExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/cache/CacheInstruction.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/FakeDCache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/storepipe/StorePipe.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Composer.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/FIFO.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/FDP.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StreamPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
scala/xiangshan/XSTester.scala
/XiangShan/utility
/XiangShan/yunsuan
4b40434c15-May-2024 zhanglinjuan <[email protected]>

Add CoupledL2 with CHI interface (#2953)

This pull request introduces TL2CHICoupledL2, which adopts TileLink
standard to connect L1 DCache/ICache/PTW, and CHI Issue B specification
to connect down

Add CoupledL2 with CHI interface (#2953)

This pull request introduces TL2CHICoupledL2, which adopts TileLink
standard to connect L1 DCache/ICache/PTW, and CHI Issue B specification
to connect downstream interconnect. The key features of TL2CHICoupledL2
are:
* Fully coherent Request Node in a CHI interconnect.
* Coherency granule of 64B cache line.
* MESI cache coherence model, which is based on TileLink coherence
policies.
* Transition from TL-C transactions to CHI snoopable requests.
* Transition from TL-UL transactions to CHI non-snoopable requests.
* Support for ReadNoSnp, ReadNotSharedDirty, ReadUnique, MakeUnique.
* Support for WriteNoSnp, WriteBackFull, Evict.
* Support for all the snoops except for SnpDVMOp.
* Request retry to manage protocol resources.
* Message transfer across CHI interfaces based on Link Layer Credit.
* Power aware signaling on the component interface.

The original CoupledL2 is now renamed to TL2TLCoupledL2. TL2TLCoupledL2
still works as default L2 Cache instance in
[XiangShan](https://github.com/OpenXiangShan/XiangShan) processor for
now. TL2CHICoupledL2 is still not available for verilator simulation in
this pr.

To compile XSTile verilog with TL2CHICoupledL2, run `make verilog
CONFIG=KunminghuV2Config RELEASE_ARGS MFC=1`.

---------

Signed-off-by: Yangyu Chen <[email protected]>
Co-authored-by: Zhu Yu <[email protected]>
Co-authored-by: Tang Haojin <[email protected]>
Co-authored-by: Yangyu Chen <[email protected]>

show more ...


/XiangShan/.github/workflows/check_verilog.py
/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/nightly.yml
/XiangShan/.gitignore
/XiangShan/Makefile
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/huancun
/XiangShan/ready-to-run
/XiangShan/src/main/scala/device/AXI4UART.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/utils/LogUtils.scala
/XiangShan/src/main/scala/utils/PipeWithFlush.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/DbEntry.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFReadArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFWBConflictChecker.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RdConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WakeUpConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiterParams.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbFuBusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FpNonPipedFuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FpPipedFuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/FuBusyTableWrite.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/ImmExtractor.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/MultiWakeupQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/PregParams.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/cache/CacheInstruction.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/FakeDCache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/storepipe/StorePipe.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/FDP.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StreamPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/PrefetcherMonitor.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/package.scala
scala/top/SimTop.scala
/XiangShan/utility
/XiangShan/yunsuan
81cbff0717-Apr-2024 chengguanghui <[email protected]>

FU: fix mgu for body elements's agnostic

* Modify the signal names about divided vector elements to be consistent with RVV Spec.


/XiangShan/.github/ISSUE_TEMPLATE/1-bug_report.md
/XiangShan/.github/ISSUE_TEMPLATE/2-feature_request.md
/XiangShan/.github/ISSUE_TEMPLATE/3-problem.md
/XiangShan/.github/ISSUE_TEMPLATE/4-other_question.md
/XiangShan/.github/ISSUE_TEMPLATE/config.yml
/XiangShan/.github/workflows/emu.yml
/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/fudian
/XiangShan/huancun
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/vlsi_mem_gen
/XiangShan/scripts/xiangshan.py
/XiangShan/src/chisel/main/scala/top/XiangShanStage.scala
/XiangShan/src/main/scala/device/AXI4Memory.scala
/XiangShan/src/main/scala/device/AXI4UART.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Generator.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/utils/ClockGate.scala
/XiangShan/src/main/scala/utils/PipeWithFlush.scala
/XiangShan/src/main/scala/utils/Trigger.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSDts.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/LsInfo.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/MemCtrl.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataSource.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/Og2ForVector.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFReadArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFWBConflictChecker.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/Instructions.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntFPToVec.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/Trigger.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/ByteMaskTailGen.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecNonPipedFuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/BranchUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/AgeDetector.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqPolicy.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/FuBusyTableWrite.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/ImmExtractor.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/MultiWakeupQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/NewAgeDetector.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/PregParams.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/ExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobDeqPtrWrapper.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobEnqPtrWrapper.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/FakeDCache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLBMissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TlbPrefetch.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBankedArray.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/FreeList.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StreamPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/DatamoduleResultBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/StorePrefetchBursts.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VLFlowQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VLUopQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSFlowQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSUopQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/main/scala/xiangshan/transforms/NestedPrefixModulesAnnotation.scala
scala/xiangshan/backend/fu/vector/ByteMaskTailGenTest.scala
/XiangShan/utility
/XiangShan/yunsuan
0c7ebb5804-Dec-2023 xiaofeibao-xjtu <[email protected]>

WakeupQueue: pdest copy


/XiangShan/Makefile
/XiangShan/src/main/scala/utils/ClockGate.scala
/XiangShan/src/main/scala/utils/PipeWithFlush.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/MemCtrl.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WakeUpConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntFPToVec.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgtu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecNonPipedFuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIDiv.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/AgeDetector.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/CancelNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/FuBusyTableRead.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/FuBusyTableWrite.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/ImmExtractor.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/MultiWakeupQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/NewAgeDetector.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VLFlowQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VLUopQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VLWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSFlowQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSUopQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
scala/xiangshan/backend/issue/MultiWakeupQueueMain.scala
scala/xiangshan/utils/GenPipeWithFlush.scala
/XiangShan/yunsuan
aab688f427-Dec-2023 Xuan Hu <[email protected]>

Merge remote-tracking branch 'upstream/kunminghu' into tmp-backend-merge-master


/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/difftest
/XiangShan/scripts/top-down/.gitignore
/XiangShan/scripts/top-down/README.md
/XiangShan/scripts/top-down/configs.py
/XiangShan/scripts/top-down/draw.py
/XiangShan/scripts/top-down/resources/spec06_rv64gcb_o2_20m.json
/XiangShan/scripts/top-down/top_down.py
/XiangShan/scripts/top-down/utils.py
/XiangShan/src/main/scala/device/AXI4DummySD.scala
/XiangShan/src/main/scala/device/AXI4Flash.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/LsInfo.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VLFlowQueue.scala
scala/top/SimTop.scala
/XiangShan/utility
fad4805824-Dec-2023 Yinan Xu <[email protected]>

Bump difftest (#2579)


/XiangShan/Makefile
/XiangShan/README.md
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/huancun
/XiangShan/scripts/top-down/.gitignore
/XiangShan/scripts/top-down/README.md
/XiangShan/scripts/top-down/configs.py
/XiangShan/scripts/top-down/draw.py
/XiangShan/scripts/top-down/resources/spec06_rv64gcb_o2_20m.json
/XiangShan/scripts/top-down/top_down.py
/XiangShan/scripts/top-down/utils.py
/XiangShan/src/main/scala/device/AXI4DummySD.scala
/XiangShan/src/main/scala/device/AXI4Flash.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/utils/PerfCounterUtils.scala
/XiangShan/src/main/scala/utils/Trigger.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Composer.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
scala/top/SimTop.scala
/XiangShan/utility
8241cb8517-Dec-2023 Xuan Hu <[email protected]>

Merge remote-tracking branch 'upstream/master' into backendq


/XiangShan/.github/CODEOWNERS
/XiangShan/.github/workflows/emu.yml
/XiangShan/Makefile
/XiangShan/README.md
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/huancun
/XiangShan/readme.zh-cn.md
/XiangShan/scripts/sram_size_collect.py
/XiangShan/scripts/xiangshan.py
/XiangShan/src/chisel/main/scala/top/XiangShanStage.scala
/XiangShan/src/chisel/main/scala/xiangshan/transforms/Helpers.scala
/XiangShan/src/chisel/main/scala/xiangshan/transforms/PrintControl.scala
/XiangShan/src/chisel/main/scala/xiangshan/transforms/PrintModuleName.scala
/XiangShan/src/chisel/main/scala/xiangshan/types.scala
/XiangShan/src/chisel/test/scala/xiangshan/types.scala
/XiangShan/src/chisel3/main/scala/top/XiangShanStage.scala
/XiangShan/src/chisel3/main/scala/xiangshan/transforms/PrintControl.scala
/XiangShan/src/chisel3/main/scala/xiangshan/transforms/PrintModuleName.scala
/XiangShan/src/chisel3/main/scala/xiangshan/types.scala
/XiangShan/src/chisel3/test/scala/xiangshan/types.scala
/XiangShan/src/main/scala/device/AXI4Memory.scala
/XiangShan/src/main/scala/device/AXI4RAM.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Generator.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/utils/ClockGate.scala
/XiangShan/src/main/scala/utils/PerfCounterUtils.scala
/XiangShan/src/main/scala/utils/Trigger.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSDts.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Vsetu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToVec.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/FakeDCache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Composer.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBankedArray.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/main/scala/xiangshan/transforms/PrintControl.scala
scala/fu/IntDiv.scala
scala/top/SimTop.scala
scala/xiangshan/DecodeTest.scala
/XiangShan/utility
f7af4c7417-Nov-2023 chengguanghui <[email protected]>

Debug Module: cherry-pick debug module from nanhu


/XiangShan/build.sc
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/device/RocketDebugWrapper.scala
/XiangShan/src/main/scala/top/BusPerfMonitor.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/utils/BitsUtils.scala
/XiangShan/src/main/scala/utils/MathUtils.scala
/XiangShan/src/main/scala/utils/Trigger.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/LsInfo.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/OldestFirstArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFReadArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbFuBusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToVec.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSR/CSRNamedConstant.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/DebugCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/Trigger.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/ByteMaskTailGen.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/CancelNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Snapshot.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/FDP.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VLFlowQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VLUopQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VLWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSFlowQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSUopQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
scala/top/SimTop.scala
/XiangShan/utility
/XiangShan/yunsuan
5931ace326-Oct-2023 Tang Haojin <[email protected]>

refactor directory hierarchy for two chisel versions (#2423)

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