Searched defs:difftest (Results 1 – 11 of 11) sorted by relevance
| /XiangShan/src/main/scala/xiangshan/backend/datapath/ |
| H A D | WbArbiter.scala | 394 val difftest = DifftestModule(new DiffIntWriteback(IntPhyRegs)) constant
404 val difftest = DifftestModule(new DiffFpWriteback(FpPhyRegs)) constant
414 val difftest = DifftestModule(new DiffVecWriteback(VfPhyRegs)) constant
425 val difftest = DifftestModule(new DiffVecV0Writeback(V0PhyRegs)) constant
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| /XiangShan/src/test/scala/top/ |
| H A D | SimTop.scala | 91 val difftest = DifftestModule.finish("XiangShan") constant
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| /XiangShan/src/main/scala/xiangshan/mem/pipeline/ |
| H A D | AtomicsUnit.scala | 541 val difftest = DifftestModule(new DiffAtomicEvent) constant
555 val difftest = DifftestModule(new DiffLrScEvent) constant
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| /XiangShan/src/main/scala/xiangshan/frontend/icache/ |
| H A D | ICacheMissUnit.scala | 461 val difftest = DifftestModule(new DiffRefillEvent, dontCare = true) constant
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| /XiangShan/src/main/scala/xiangshan/mem/sbuffer/ |
| H A D | Sbuffer.scala | 762 val difftest = DifftestModule(new DiffSbufferEvent, delay = 1) constant
975 val difftest = DifftestModule(new DiffStoreEvent, delay = 2, dontCare = true) constant
996 val difftest = DifftestModule(new DiffStoreEvent, delay = 2, dontCare = true) constant
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| /XiangShan/src/main/scala/xiangshan/backend/fu/ |
| H A D | CSR.scala | 1565 val difftest = DifftestModule(new DiffArchEvent, delay = 3, dontCare = true) constant
1578 val difftest = DifftestModule(new DiffCSRState) constant
1601 val difftest = DifftestModule(new DiffHCSRState) constant
1623 val difftest = DifftestModule(new DiffDebugMode) constant
1633 val difftest = DifftestModule(new DiffVecCSRState) constant
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| /XiangShan/src/main/scala/xiangshan/cache/mmu/ |
| H A D | L2TLB.scala | 545 val difftest = DifftestModule(new DiffRefillEvent, dontCare = true) constant
556 val difftest = DifftestModule(new DiffL2TLBEvent) constant
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| H A D | TLB.scala | 687 val difftest = DifftestModule(new DiffL1TLBEvent) constant
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/ |
| H A D | Uncache.scala | 439 val difftest = DifftestModule(new DiffUncacheMMStoreEvent, delay = 1) constant
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| /XiangShan/src/main/scala/xiangshan/backend/rob/ |
| H A D | Rob.scala | 1508 val difftest = DifftestModule(new DiffInstrCommit(MaxPhyRegs), delay = 3, dontCare = true) constant
1561 val difftest = DifftestModule(new DiffTrapEvent, dontCare = true) constant
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/ |
| H A D | MissQueue.scala | 1176 val difftest = DifftestModule(new DiffRefillEvent, dontCare = true) constant
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