Searched defs:s1_ready (Results 1 – 9 of 9) sorted by relevance
/XiangShan/src/main/scala/xiangshan/frontend/icache/ |
H A D | ICacheMainPipe.scala | 152 val s1_ready, s2_ready = Wire(Bool()) constant
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/XiangShan/src/main/scala/xiangshan/backend/datapath/ |
H A D | DataPath.scala | 584 val s1_ready = s1_toExuReady(i)(j) constant
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/XiangShan/src/main/scala/xiangshan/mem/pipeline/ |
H A D | StoreUnit.scala | 79 val s1_ready, s2_ready, s3_ready = WireInit(false.B) constant
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H A D | HybridUnit.scala | 165 val s1_ready, s2_ready, s3_ready, sx_can_go = WireInit(false.B) constant
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H A D | LoadUnit.scala | 217 val s1_ready, s2_ready, s3_ready = WireInit(false.B) constant
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/XiangShan/src/main/scala/xiangshan/mem/vector/ |
H A D | VSplit.scala | 43 val s1_ready = WireInit(false.B) constant
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/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/ |
H A D | LoadPipe.scala | 115 val s1_ready = Wire(Bool()) constant
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/XiangShan/src/main/scala/xiangshan/frontend/ |
H A D | BPU.scala | 163 val s1_ready = Output(Bool()) constant
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/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/ |
H A D | MainPipe.scala | 221 val s1_ready, s2_ready, s3_ready = Wire(Bool()) constant
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