Home
last modified time | relevance | path

Searched full:display (Results 1 – 25 of 3455) sorted by relevance

12345678910>>...139

/linux-6.14.4/drivers/gpu/drm/i915/display/
Dintel_display_driver.c5 * High level display driver entry points. This is a layer between top level
6 * driver code and low level display functionality; no low level display code or
12 #include <drm/display/drm_dp_mst_helper.h>
83 void intel_display_driver_init_hw(struct intel_display *display) in intel_display_driver_init_hw() argument
85 struct drm_i915_private *i915 = to_i915(display->drm); in intel_display_driver_init_hw()
88 if (!HAS_DISPLAY(display)) in intel_display_driver_init_hw()
91 cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state); in intel_display_driver_init_hw()
93 intel_update_cdclk(display); in intel_display_driver_init_hw()
94 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); in intel_display_driver_init_hw()
95 cdclk_state->logical = cdclk_state->actual = display->cdclk.hw; in intel_display_driver_init_hw()
[all …]
Di9xx_display_sr.c15 static void i9xx_display_save_swf(struct intel_display *display) in i9xx_display_save_swf() argument
20 if (DISPLAY_VER(display) == 2 && display->platform.mobile) { in i9xx_display_save_swf()
22 display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i)); in i9xx_display_save_swf()
23 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
26 display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i)); in i9xx_display_save_swf()
27 } else if (DISPLAY_VER(display) == 2) { in i9xx_display_save_swf()
29 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
30 } else if (HAS_GMCH(display)) { in i9xx_display_save_swf()
32 display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i)); in i9xx_display_save_swf()
33 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
[all …]
Dintel_display_power.c201 static bool __intel_display_power_is_enabled(struct intel_display *display, in __intel_display_power_is_enabled() argument
207 if (pm_runtime_suspended(display->drm->dev)) in __intel_display_power_is_enabled()
212 for_each_power_domain_well_reverse(display, power_well, domain) { in __intel_display_power_is_enabled()
245 struct intel_display *display = &dev_priv->display; in intel_display_power_is_enabled() local
246 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_is_enabled()
250 ret = __intel_display_power_is_enabled(display, domain); in intel_display_power_is_enabled()
257 sanitize_target_dc_state(struct intel_display *display, in sanitize_target_dc_state() argument
260 struct i915_power_domains *power_domains = &display->power.domains; in sanitize_target_dc_state()
284 * @display: display device
291 void intel_display_power_set_target_dc_state(struct intel_display *display, in intel_display_power_set_target_dc_state() argument
[all …]
Dintel_display_power_well.c49 void (*sync_hw)(struct intel_display *display,
56 void (*enable)(struct intel_display *display,
62 void (*disable)(struct intel_display *display,
65 bool (*is_enabled)(struct intel_display *display,
76 lookup_power_well(struct intel_display *display, in lookup_power_well() argument
81 for_each_power_well(display, power_well) in lookup_power_well()
88 * to abort things like display initialization sequences. Just return in lookup_power_well()
92 drm_WARN(display->drm, 1, in lookup_power_well()
95 return &display->power.domains.power_wells[0]; in lookup_power_well()
98 void intel_power_well_enable(struct intel_display *display, in intel_power_well_enable() argument
[all …]
Dintel_gmbus.c34 #include <drm/display/drm_hdcp_helper.h>
51 struct intel_display *display; member
152 static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display, in get_gmbus_pin() argument
155 struct drm_i915_private *i915 = to_i915(display->drm); in get_gmbus_pin()
177 } else if (DISPLAY_VER(display) == 9) { in get_gmbus_pin()
194 bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin) in intel_gmbus_is_valid_pin() argument
196 return get_gmbus_pin(display, pin); in intel_gmbus_is_valid_pin()
210 intel_gmbus_reset(struct intel_display *display) in intel_gmbus_reset() argument
212 intel_de_write(display, GMBUS0(display), 0); in intel_gmbus_reset()
213 intel_de_write(display, GMBUS4(display), 0); in intel_gmbus_reset()
[all …]
Dintel_de.h16 static inline struct intel_uncore *__to_uncore(struct intel_display *display) in __to_uncore() argument
18 return to_intel_uncore(display->drm); in __to_uncore()
22 __intel_de_read(struct intel_display *display, i915_reg_t reg) in __intel_de_read() argument
26 intel_dmc_wl_get(display, reg); in __intel_de_read()
28 val = intel_uncore_read(__to_uncore(display), reg); in __intel_de_read()
30 intel_dmc_wl_put(display, reg); in __intel_de_read()
37 intel_de_read8(struct intel_display *display, i915_reg_t reg) in intel_de_read8() argument
41 intel_dmc_wl_get(display, reg); in intel_de_read8()
43 val = intel_uncore_read8(__to_uncore(display), reg); in intel_de_read8()
45 intel_dmc_wl_put(display, reg); in intel_de_read8()
[all …]
Dintel_cdclk.c55 * The display engine uses several different clocks to do its work. There
58 * are the core display clock (CDCLK) and RAWCLK.
60 * CDCLK clocks most of the display pipe logic, and thus its frequency
66 * to minimize power consumption for a given display configuration.
67 * Typically changes to the CDCLK frequency require all the display pipes
117 void (*get_cdclk)(struct intel_display *display,
119 void (*set_cdclk)(struct intel_display *display,
126 void intel_cdclk_get_cdclk(struct intel_display *display, in intel_cdclk_get_cdclk() argument
129 display->funcs.cdclk->get_cdclk(display, cdclk_config); in intel_cdclk_get_cdclk()
132 static void intel_cdclk_set_cdclk(struct intel_display *display, in intel_cdclk_set_cdclk() argument
[all …]
Dintel_dmc.c38 * From gen9 onwards we have newly added DMC (Display microcontroller) in display
39 * engine to save and restore the state of display engine when it enter into
55 struct intel_display *display; member
73 static struct intel_dmc *display_to_dmc(struct intel_display *display) in display_to_dmc() argument
75 return display->dmc.dmc; in display_to_dmc()
78 static const char *dmc_firmware_param(struct intel_display *display) in dmc_firmware_param() argument
80 const char *p = display->params.dmc_firmware_path; in dmc_firmware_param()
85 static bool dmc_firmware_param_disabled(struct intel_display *display) in dmc_firmware_param_disabled() argument
87 const char *p = dmc_firmware_param(display); in dmc_firmware_param_disabled()
168 static const char *dmc_firmware_default(struct intel_display *display, u32 *size) in dmc_firmware_default() argument
[all …]
Dintel_pps.c23 static void vlv_steal_power_sequencer(struct intel_display *display,
31 struct intel_display *display = to_intel_display(intel_dp); in pps_name() local
34 if (display->platform.valleyview || display->platform.cherryview) { in pps_name()
67 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_lock() local
68 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_pps_lock()
75 mutex_lock(&display->pps.mutex); in intel_pps_lock()
83 struct intel_display *display = to_intel_display(intel_dp); in intel_pps_unlock() local
84 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_pps_unlock()
86 mutex_unlock(&display->pps.mutex); in intel_pps_unlock()
95 struct intel_display *display = to_intel_display(intel_dp); in vlv_power_sequencer_kick() local
[all …]
Dintel_vrr.c19 struct intel_display *display = to_intel_display(connector); in intel_vrr_is_capable() local
45 return HAS_VRR(display) && in intel_vrr_is_capable()
96 struct intel_display *display = to_intel_display(crtc_state); in intel_vrr_vblank_exit_length() local
98 if (DISPLAY_VER(display) >= 13) in intel_vrr_vblank_exit_length()
119 struct intel_display *display = to_intel_display(crtc_state); in is_cmrr_frac_required() local
123 if (!HAS_CMRR(display)) in is_cmrr_frac_required()
167 struct intel_display *display = to_intel_display(crtc_state); in intel_vrr_compute_config() local
191 if (HAS_LRR(display)) in intel_vrr_compute_config()
250 struct intel_display *display = to_intel_display(crtc_state); in intel_vrr_compute_config_late() local
256 if (DISPLAY_VER(display) >= 13) { in intel_vrr_compute_config_late()
[all …]
Dintel_hdcp.c15 #include <drm/display/drm_hdcp_helper.h>
39 struct intel_display *display = to_intel_display(encoder); in intel_hdcp_adjust_hdcp_line_rekeying() local
47 if (DISPLAY_VER(display) >= 30) { in intel_hdcp_adjust_hdcp_line_rekeying()
48 rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); in intel_hdcp_adjust_hdcp_line_rekeying()
50 } else if (IS_DISPLAY_VERx100_STEP(display, 1401, STEP_B0, STEP_FOREVER) || in intel_hdcp_adjust_hdcp_line_rekeying()
51 IS_DISPLAY_VERx100_STEP(display, 2000, STEP_B0, STEP_FOREVER)) { in intel_hdcp_adjust_hdcp_line_rekeying()
52 rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); in intel_hdcp_adjust_hdcp_line_rekeying()
54 } else if (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_D0, STEP_FOREVER)) { in intel_hdcp_adjust_hdcp_line_rekeying()
55 rekey_reg = CHICKEN_TRANS(display, hdcp->cpu_transcoder); in intel_hdcp_adjust_hdcp_line_rekeying()
60 intel_de_rmw(display, rekey_reg, rekey_bit, enable ? 0 : rekey_bit); in intel_hdcp_adjust_hdcp_line_rekeying()
[all …]
Dintel_fbc.c28 * compressing the amount of memory used by the display. It is total
33 * and having fewer memory pages opened and accessed for refreshing the display.
94 struct intel_display *display; member
158 static unsigned int skl_fbc_min_cfb_stride(struct intel_display *display, in skl_fbc_min_cfb_stride() argument
172 if (DISPLAY_VER(display) >= 11) in skl_fbc_min_cfb_stride()
186 static unsigned int _intel_fbc_cfb_stride(struct intel_display *display, in _intel_fbc_cfb_stride() argument
195 if (DISPLAY_VER(display) >= 9) in _intel_fbc_cfb_stride()
196 return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(display, cpp, width)); in _intel_fbc_cfb_stride()
203 struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev); in intel_fbc_cfb_stride() local
208 return _intel_fbc_cfb_stride(display, cpp, width, stride); in intel_fbc_cfb_stride()
[all …]
Dvlv_dsi_regs.h14 #define _MIPI_MMIO_BASE(display) ((display)->dsi.mmio_base) argument
97 #define MIPI_DEVICE_READY(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DEVICE_R… argument
107 #define MIPI_INTR_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT,… argument
110 #define MIPI_INTR_EN(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN, _MI… argument
146 #define MIPI_DSI_FUNC_PRG(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DSI_FUNC… argument
169 #define MIPI_HS_TX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HS_TX_T… argument
174 #define MIPI_LP_RX_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_LP_RX_T… argument
179 #define MIPI_TURN_AROUND_TIMEOUT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_T… argument
184 #define MIPI_DEVICE_RESET_TIMER(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DE… argument
189 #define MIPI_DPI_RESOLUTION(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_RE… argument
[all …]
Dintel_psr.c52 * Since Haswell Display controller supports Panel Self-Refresh on display
54 * spec in eDP1.3. PSR feature allows the display to go to lower standby states
55 * when system is idle but display is on as it eliminates display refresh
57 * display is unchanged.
101 * When unmasked (nearly) all display register writes (eg. even
230 struct intel_display *display = to_intel_display(intel_dp); in psr_global_enabled() local
235 if (display->params.enable_psr == -1) in psr_global_enabled()
239 return display->params.enable_psr; in psr_global_enabled()
249 struct intel_display *display = to_intel_display(intel_dp); in psr2_global_enabled() local
256 if (display->params.enable_psr == 1) in psr2_global_enabled()
[all …]
Dvlv_dsi.c89 struct intel_display *display = to_intel_display(&intel_dsi->base); in vlv_dsi_wait_for_fifo_empty() local
95 if (intel_de_wait_for_set(display, MIPI_GEN_FIFO_STAT(display, port), in vlv_dsi_wait_for_fifo_empty()
97 drm_err(display->drm, "DPI FIFOs are not empty\n"); in vlv_dsi_wait_for_fifo_empty()
100 static void write_data(struct intel_display *display, in write_data() argument
112 intel_de_write(display, reg, val); in write_data()
116 static void read_data(struct intel_display *display, in read_data() argument
123 u32 val = intel_de_read(display, reg); in read_data()
135 struct intel_display *display = to_intel_display(&intel_dsi->base); in intel_dsi_host_transfer() local
150 data_reg = MIPI_LP_GEN_DATA(display, port); in intel_dsi_host_transfer()
152 ctrl_reg = MIPI_LP_GEN_CTRL(display, port); in intel_dsi_host_transfer()
[all …]
Dintel_pmdemand.c78 struct intel_display *display = to_intel_display(state); in intel_atomic_get_pmdemand_state() local
81 &display->pmdemand.obj); in intel_atomic_get_pmdemand_state()
92 struct intel_display *display = to_intel_display(state); in intel_atomic_get_old_pmdemand_state() local
95 &display->pmdemand.obj); in intel_atomic_get_old_pmdemand_state()
106 struct intel_display *display = to_intel_display(state); in intel_atomic_get_new_pmdemand_state() local
109 &display->pmdemand.obj); in intel_atomic_get_new_pmdemand_state()
117 int intel_pmdemand_init(struct intel_display *display) in intel_pmdemand_init() argument
125 intel_atomic_global_obj_init(display, &display->pmdemand.obj, in intel_pmdemand_init()
129 if (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_C0)) in intel_pmdemand_init()
131 intel_de_rmw(display, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE); in intel_pmdemand_init()
[all …]
Dintel_bios.c31 #include <drm/display/drm_dp_helper.h>
32 #include <drm/display/drm_dsc_helper.h>
51 * through other means. The configuration is mostly related to display
70 struct intel_display *display; member
149 bdb_find_section(struct intel_display *display, in bdb_find_section() argument
154 list_for_each_entry(entry, &display->vbt.bdb_blocks, node) { in bdb_find_section()
204 static size_t lfp_data_min_size(struct intel_display *display) in lfp_data_min_size() argument
209 ptrs = bdb_find_section(display, BDB_LFP_DATA_PTRS); in lfp_data_min_size()
364 static void *generate_lfp_data_ptrs(struct intel_display *display, in generate_lfp_data_ptrs() argument
378 if (display->vbt.version < 155) in generate_lfp_data_ptrs()
[all …]
Dintel_opregion.c85 u32 didl[8]; /* supported display devices ID list */
86 u32 cpdl[8]; /* currently presented display list */
87 u32 cadl[8]; /* currently active display list */
98 u32 did2[7]; /* extended supported display devices ID list */
99 u32 cpd2[7]; /* extended attached display devices list */
256 struct intel_display *display; member
272 static int check_swsci_function(struct intel_display *display, u32 function) in check_swsci_function() argument
274 struct intel_opregion *opregion = display->opregion; in check_swsci_function()
304 static int swsci(struct intel_display *display, in swsci() argument
308 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in swsci()
[all …]
Dicl_dsi.c28 #include <drm/display/drm_dsc_helper.h>
56 static int header_credits_available(struct intel_display *display, in header_credits_available() argument
59 return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) in header_credits_available()
63 static int payload_credits_available(struct intel_display *display, in payload_credits_available() argument
66 return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) in payload_credits_available()
70 static bool wait_for_header_credits(struct intel_display *display, in wait_for_header_credits() argument
73 if (wait_for_us(header_credits_available(display, dsi_trans) >= in wait_for_header_credits()
75 drm_err(display->drm, "DSI header credits not released\n"); in wait_for_header_credits()
82 static bool wait_for_payload_credits(struct intel_display *display, in wait_for_payload_credits() argument
85 if (wait_for_us(payload_credits_available(display, dsi_trans) >= in wait_for_payload_credits()
[all …]
Dintel_crt.c90 bool intel_crt_port_enabled(struct intel_display *display, in intel_crt_port_enabled() argument
93 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_crt_port_enabled()
96 val = intel_de_read(display, adpa_reg); in intel_crt_port_enabled()
110 struct intel_display *display = to_intel_display(encoder); in intel_crt_get_hw_state() local
121 ret = intel_crt_port_enabled(display, crt->adpa_reg, pipe); in intel_crt_get_hw_state()
130 struct intel_display *display = to_intel_display(encoder); in intel_crt_get_flags() local
134 tmp = intel_de_read(display, crt->adpa_reg); in intel_crt_get_flags()
179 struct intel_display *display = to_intel_display(encoder); in intel_crt_set_dpms() local
186 if (DISPLAY_VER(display) >= 5) in intel_crt_set_dpms()
205 intel_de_write(display, BCLRPAT(display, crtc->pipe), 0); in intel_crt_set_dpms()
[all …]
Dintel_opregion.h37 int intel_opregion_setup(struct intel_display *display);
38 void intel_opregion_cleanup(struct intel_display *display);
40 void intel_opregion_register(struct intel_display *display);
41 void intel_opregion_unregister(struct intel_display *display);
43 void intel_opregion_resume(struct intel_display *display);
44 void intel_opregion_suspend(struct intel_display *display,
47 bool intel_opregion_asle_present(struct intel_display *display);
48 void intel_opregion_asle_intr(struct intel_display *display);
51 int intel_opregion_notify_adapter(struct intel_display *display,
53 int intel_opregion_get_panel_type(struct intel_display *display);
[all …]
/linux-6.14.4/drivers/gpu/drm/i915/
DMakefile12 # Support compiling the display code separately for both i915 and xe
222 display/hsw_ips.o \
223 display/i9xx_plane.o \
224 display/i9xx_display_sr.o \
225 display/i9xx_wm.o \
226 display/intel_alpm.o \
227 display/intel_atomic.o \
228 display/intel_atomic_plane.o \
229 display/intel_audio.o \
230 display/intel_bios.o \
[all …]
/linux-6.14.4/drivers/gpu/drm/xe/
DMakefile151 # i915 Display compat #defines and #includes
153 -I$(src)/display/ext \
155 -I$(srctree)/drivers/gpu/drm/i915/display/ \
163 # Rule to build display code shared with i915
164 $(obj)/i915-display/%.o: $(srctree)/drivers/gpu/drm/i915/display/%.c FORCE
168 # Display code specific to xe
170 display/ext/i915_irq.o \
171 display/ext/i915_utils.o \
172 display/intel_bo.o \
173 display/intel_fb_bo.o \
[all …]
/linux-6.14.4/drivers/gpu/drm/xe/display/
Dxe_display.c38 return HAS_DISPLAY(&xe->display); in has_display()
57 * xe_display_driver_set_hooks - Add driver flags and hooks for display
61 * display IP. This sets the driver's capability of driving display, regardless
81 destroy_workqueue(xe->display.hotplug.dp_wq); in display_destroy()
85 * xe_display_create - create display struct
88 * Initialize all fields used by the display part.
91 * to the rest of xe and return it to be xe->display.
97 spin_lock_init(&xe->display.fb_tracking.lock); in xe_display_create()
99 xe->display.hotplug.dp_wq = alloc_ordered_workqueue("xe-dp", 0); in xe_display_create()
107 struct intel_display *display = &xe->display; in xe_display_fini_nommio() local
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/display/
Dallwinner,sun4i-a10-display-engine.yaml4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-engine.yaml#
7 title: Allwinner A10 Display Engine Pipeline
14 The display engine pipeline (and its entry point, since it can be
18 The Allwinner A10 Display pipeline is composed of several components
22 display pipeline, when there are multiple components of the same
52 - allwinner,sun4i-a10-display-engine
53 - allwinner,sun5i-a10s-display-engine
54 - allwinner,sun5i-a13-display-engine
55 - allwinner,sun6i-a31-display-engine
56 - allwinner,sun6i-a31s-display-engine
[all …]

12345678910>>...139