| /XiangShan/src/main/scala/xiangshan/mem/ |
| H A D | MemTrace.scala | 26 val source = UInt(4.W) constant
|
| H A D | MemBlock.scala | 459 val source = loadUnits(i).io.prefetch_train_l1 constant
472 val source = hybridUnits(i).io.prefetch_train_l1 constant
934 val source = loadUnits(i).io.prefetch_train constant
949 val source = loadUnits(i).io.prefetch_train_l1 constant
1072 val source = hybridUnits(i).io.prefetch_train constant
1082 val source = hybridUnits(i).io.prefetch_train_l1 constant
1090 val source = hybridUnits(i).io.prefetch_train constant
|
| /XiangShan/src/main/scala/xiangshan/cache/mmu/ |
| H A D | PageTableWalker.scala | 59 val source = UInt(bSourceWidth.W) constant
71 val source = UInt(bSourceWidth.W) constant
180 val source = RegEnable(io.req.bits.req_info.source, io.req.fire) constant
674 val source = UInt(bSourceWidth.W) constant
1027 val source = UInt(bSourceWidth.W) constant
1109 val source = UInt(bSourceWidth.W) constant
1128 val source = UInt(bSourceWidth.W) constant
1230 val source = RegEnable(io.req.bits.source, io.req.fire) constant
|
| H A D | MMUBundle.scala | 1359 val source = UInt(bSourceWidth.W) constant
1385 val source = UInt(bSourceWidth.W) constant
1397 val source = UInt(bSourceWidth.W) constant
|
| H A D | L2TLB.scala | 131 val source = UInt(bSourceWidth.W) constant
|
| /XiangShan/src/main/scala/xiangshan/backend/issue/ |
| H A D | BypassNetwork.scala | 34 val source = Vec(numWays, Input(UInt(dataBits.W))) constant
|
| /XiangShan/src/main/scala/xiangshan/mem/prefetch/ |
| H A D | BasePrefecher.scala | 60 val source = UInt(MemReqSource.reqSourceBits.W) constant
|
| H A D | L1StreamPrefetcher.scala | 117 val source = new L1PrefetchSource() constant
|
| H A D | L1PrefetchComponent.scala | 263 val source = new L1PrefetchSource() constant
|
| /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/ |
| H A D | Probe.scala | 28 val source = UInt() constant
|
| H A D | MissQueue.scala | 48 val source = UInt(sourceTypeWidth.W) constant
|
| H A D | MainPipe.scala | 45 val source = UInt(sourceTypeWidth.W) constant
|
| /XiangShan/src/main/scala/xiangshan/ |
| H A D | XSTileWrap.scala | 149 … val source = withClockAndReset(clock, noc_reset_sync.get)(Module(new CHIAsyncBridgeSource(param))) constant
|
| H A D | Bundle.scala | 700 val source = Output(new Bundle() { constant
|
| /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/ |
| H A D | AsynchronousMetaArray.scala | 168 val source = UInt(L1PfSourceBits.W) constant
|
| /XiangShan/src/main/scala/xiangshan/backend/exu/ |
| H A D | ExeUnit.scala | 276 val source = inPipe._1(i) constant
|
| /XiangShan/src/main/scala/top/ |
| H A D | XSNoCTop.scala | 324 val source = Module(new AsyncQueueSource(UInt(64.W), param)) constant
|
| /XiangShan/src/main/scala/xiangshan/cache/dcache/ |
| H A D | DCacheWrapper.scala | 582 val source = UInt(sourceTypeWidth.W) constant
|