| /XiangShan/src/main/scala/xiangshan/cache/wpu/ |
| H A D | WPUWrapper.scala | 13 val valid = Bool() constant
237 val valid = Bool() constant
241 val valid = Bool() constant
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| /XiangShan/src/main/scala/xiangshan/backend/issue/ |
| H A D | WakeupQueue.scala | 41 val valid = Bool() constant
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| H A D | BypassNetwork.scala | 28 val valid = Vec(numWays, Bool()) constant
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| /XiangShan/src/main/scala/xiangshan/mem/mdp/ |
| H A D | StoreSet.scala | 41 val valid = Bool() constant
329 val valid = Bool() constant
363 val valid = Wire(Vec(LFSTSize, Bool())) constant
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| /XiangShan/src/main/scala/xiangshan/backend/datapath/ |
| H A D | NewPipelineConnect.scala | 40 val valid = RegInit(false.B) constant
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| /XiangShan/src/main/scala/device/ |
| H A D | AXI4VGA.scala | 66 val valid = Output(Bool()) constant
97 val valid = IO(Input(Bool())) constant
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| H A D | AXI4Memory.scala | 266 val valid = RegInit(false.B) constant
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| /XiangShan/src/main/scala/xiangshan/mem/ |
| H A D | MemCommon.scala | 107 val valid = RegInit(false.B) constant
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| /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/ |
| H A D | TrapInstMod.scala | 42 val valid = RegInit(false.B) constant
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| /XiangShan/src/main/scala/xiangshan/backend/regcache/ |
| H A D | RegCacheTagModule.scala | 30 val valid = Output(Bool()) constant
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/ |
| H A D | Uncache.scala | 53 val valid = Output(Bool()) constant
133 val valid = Bool() constant
339 val valid = e0_req_valid && states(i).isValid() constant
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| H A D | CtrlUnit.scala | 58 val valid = Bool() constant
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| /XiangShan/src/main/scala/xiangshan/mem/vector/ |
| H A D | VfofBuffer.scala | 42 val valid = RegInit(false.B) constant
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| /XiangShan/src/main/scala/top/ |
| H A D | BusPerfMonitor.scala | 110 val valid = Bool() constant
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| /XiangShan/src/main/scala/xiangshan/frontend/ |
| H A D | ITTAGE.scala | 93 val valid = Bool() constant
134 val valid = Bool() constant
158 val valid = WireInit(valids.andR) constant
248 val valid = Bool() constant
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| H A D | FTB.scala | 49 val valid = Bool() constant
180 val valid = Bool() constant
616 val valid = WireInit(valids.andR) constant
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| H A D | FauFTB.scala | 58 val valid = RegInit(false.B) constant
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| /XiangShan/src/main/scala/xiangshan/frontend/icache/ |
| H A D | IPrefetch.scala | 321 val valid = fromMSHR.valid && !fromMSHR.bits.corrupt constant
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| /XiangShan/src/main/scala/xiangshan/backend/fu/vector/ |
| H A D | Mgu.scala | 200 val valid = Bool() constant
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| /XiangShan/src/main/scala/xiangshan/mem/lsqueue/ |
| H A D | LSQWrapper.scala | 48 val valid = Bool() // valid is generated 1 cycle after query request constant
55 val valid = Bool() constant
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| H A D | LoadMisalignBuffer.scala | 128 val valid = Bool() constant
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| H A D | StoreQueueData.scala | 94 val valid = Bool() // this byte is valid constant
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| H A D | StoreMisalignBuffer.scala | 108 val valid = Bool() constant
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| /XiangShan/src/main/scala/xiangshan/backend/rob/ |
| H A D | Rab.scala | 274 val valid = (state === s_special_walk) && vecLoadExcp.valid && io.commits.commitValid(i) constant
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| /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/ |
| H A D | CSREvent.scala | 72 val valid = IO(Input(Bool())) constant
|