fix: add low power related logic (#4554)
fix(XSNoCTop): fix wfi wakeup by snoop (#4521)* add flitpend wakeup with all rx channel instead of rx.snp* After clock is restored by flitpend, wait for Core to enter wfi againbefore gating the c
fix(XSNoCTop): fix wfi wakeup by snoop (#4521)* add flitpend wakeup with all rx channel instead of rx.snp* After clock is restored by flitpend, wait for Core to enter wfi againbefore gating the clock
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feat(XSNoCTop): Power down and WFI gating (#4373)The low-power features include the following:* when Core is in WFI state, Core+L2 clock is gated and restore clocksonly when interrupt/reset/snoo
feat(XSNoCTop): Power down and WFI gating (#4373)The low-power features include the following:* when Core is in WFI state, Core+L2 clock is gated and restore clocksonly when interrupt/reset/snoop.* low-power process is controlled by FSM to follow the steps: flush L2-> core enter WFI state -> send power-down request to SoC (o_cpu_no_op)* SoC plays as PPU to generate power on/off sequence with signals:isolation/reset/clock, also the power on/off req/ack signals
feat(XSLog): move all XSLog outside WhenContext for collectionAs data in WhenContext is not acessible in another module. To supportXSLog collection, we move all XSLog and related signal outsideWh
feat(XSLog): move all XSLog outside WhenContext for collectionAs data in WhenContext is not acessible in another module. To supportXSLog collection, we move all XSLog and related signal outsideWhenContext. For example, when(cond1){XSDebug(cond2, pable)} toXSDebug(cond1 && cond2, pable)
chore: use scala-provided `distinctBy`
fix(utils): fix AXI4LiteBundle signal connection (#3779)Reported-by: hong Zhao <[email protected]>Fixed-by: jiuyue Ma <[email protected]>Signed-off-by: yuxin Zhang <[email protected]>Si
fix(utils): fix AXI4LiteBundle signal connection (#3779)Reported-by: hong Zhao <[email protected]>Fixed-by: jiuyue Ma <[email protected]>Signed-off-by: yuxin Zhang <[email protected]>Signed-off-by: yuxin Zhang <[email protected]>
refactor(HPM): move HPMs from utils to utility repo (#3631)Because HPMs will be used in Coupled L2 as well, delete `PerfCounterUtils.scala` in Xiangshan and create `HardwarePerfMonitor.scala` in
refactor(HPM): move HPMs from utils to utility repo (#3631)Because HPMs will be used in Coupled L2 as well, delete `PerfCounterUtils.scala` in Xiangshan and create `HardwarePerfMonitor.scala` in Utility. See also [Pull Request in CoupledL2](https://github.com/OpenXiangShan/CoupledL2/pull/251#discussion_r1770738535).
Frontend,Backend: add xxtvala support* utils * Add checkInputWidth function in NamedUInt to check if the UInt arg passed in has the same width as it defined.* Frontend * Pass the unexpanded in
Frontend,Backend: add xxtvala support* utils * Add checkInputWidth function in NamedUInt to check if the UInt arg passed in has the same width as it defined.* Frontend * Pass the unexpanded instruciton to IBuffer if the C extension 16 bits instruction is illegal. * No need to use bypass illBuf, since the origin 16 bits instruction will be passed in the ctrlflow bundle. * IBuffer * Merge exceptionType and crossPageIPFFix into 3bit field, which type is IBufferExceptionType. * IBufferExceptionType can hold illegal instruction exception.* Backend * CSROpType.ro is removed, since we can use rs1 and rd passed in imm field to distinguish CSRR and CSRW in CSR module. * Create TrapInstMod to store the trap instruction and handle its update.
build: purge chisel 3 and add deprecation check (#3250)
perf: use perfUtils in `Utility` (#3190)Currently, log and perf utilities such as `XSPerfAccumulate` are implemented in many repositories like XiangShan, CoupledL2 and HuanCun. This PR unifies th
perf: use perfUtils in `Utility` (#3190)Currently, log and perf utilities such as `XSPerfAccumulate` are implemented in many repositories like XiangShan, CoupledL2 and HuanCun. This PR unifies them and put them in Utility repository.
top: implement XSNoCTop and standalone devices (#3136)
Top: use VerilogAXI4Record instead of `sed` to handle amba signal names
LogUtils: remove the unused reset condition (#2968)Chisel Assertions are checked only when reset is deasserted.
Backend: reduce the width of LoadDependency to 2 bits
Bump utility and difftest (#2901)* fix nightly CI
ClockGate: remove `@*` after `always_latch`
Trigger: optimize trigger* delete data trigger in frontend* optimiza trigger comparison logic co-author-by: Guokai Chen <[email protected]>* delete frontendTiming & frontendChain
Trigger: optimize trigger* delete data trigger in frontend* optimiza trigger comparison logic co-author-by: Guokai Chen <[email protected]>* delete frontendTiming & frontendChain in TriggerCf
Merge remote-tracking branch 'upstream/master' into tmp-backend-merge-fixtiming
wakeup: remove flush between iq and wakeup queue
backend: WBArbiter support two out at same time, fast wakeup remove valid
Backend: optimize wakeupQueue timing
WakeupQueue: pdest copy
chore: bump chisel 6.0.0 (#2654)BREAKING CHANGE: `SimTop.v` / `XSTop.v` now generated in `build/rtl`
ClockGate: modify the latch to adapt to verilator 5.218
Merge remote-tracking branch 'upstream/master' into backendq
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