History log of /XiangShan/src/main/scala/utils/ (Results 1 – 25 of 399)
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814aa9ec15-Apr-2025 yulightenyu <[email protected]>

fix: add low power related logic (#4554)


/XiangShan/ChiselAIA
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/huancun
/XiangShan/src/main/resources/config/Default.yml
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/top/YamlParser.scala
LowPowerState.scala
PowerSwitchBuffer.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TlbPrefetch.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/mem/Bundles.scala
/XiangShan/src/main/scala/xiangshan/mem/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/utility
ce80648b09-Apr-2025 yulightenyu <[email protected]>

fix(XSNoCTop): fix wfi wakeup by snoop (#4521)

* add flitpend wakeup with all rx channel instead of rx.snp
* After clock is restored by flitpend, wait for Core to enter wfi again
before gating the c

fix(XSNoCTop): fix wfi wakeup by snoop (#4521)

* add flitpend wakeup with all rx channel instead of rx.snp
* After clock is restored by flitpend, wait for Core to enter wfi again
before gating the clock

show more ...


/XiangShan/.github/CODEOWNERS
/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/nightly.yml
/XiangShan/.github/workflows/perf.yml
/XiangShan/ChiselAIA
/XiangShan/Makefile
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/ready-to-run
/XiangShan/scalastyle-config.xml
/XiangShan/scripts/perfcct.py
/XiangShan/scripts/top-down/configs.py
/XiangShan/scripts/top-down/draw.py
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/resources/config/Default.yml
/XiangShan/src/main/scala/device/AXI4Memory.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/top/YamlParser.scala
LowPowerState.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/mem/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/utility
4d7fbe7717-Mar-2025 yulightenyu <[email protected]>

feat(XSNoCTop): Power down and WFI gating (#4373)

The low-power features include the following:
* when Core is in WFI state, Core+L2 clock is gated and restore clocks
only when interrupt/reset/snoo

feat(XSNoCTop): Power down and WFI gating (#4373)

The low-power features include the following:
* when Core is in WFI state, Core+L2 clock is gated and restore clocks
only when interrupt/reset/snoop.
* low-power process is controlled by FSM to follow the steps: flush L2
-> core enter WFI state -> send power-down request to SoC (o_cpu_no_op)
* SoC plays as PPU to generate power on/off sequence with signals:
isolation/reset/clock, also the power on/off req/ack signals

show more ...


/XiangShan/.github/CODEOWNERS
/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/perf.yml
/XiangShan/.gitmodules
/XiangShan/ChiselAIA
/XiangShan/Makefile
/XiangShan/README.md
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/huancun
/XiangShan/openLLC
/XiangShan/readme.zh-cn.md
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scalastyle-config.xml
/XiangShan/scalastyle-test-config.xml
/XiangShan/scripts/constantHelper.py
/XiangShan/scripts/requirements.txt
/XiangShan/scripts/rolling/.gitignore
/XiangShan/scripts/rolling/rollingplot.py
/XiangShan/scripts/top-down/configs.py
/XiangShan/scripts/top-down/top_down.py
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/resources/config/Default.yml
/XiangShan/src/main/scala/device/AXI4Memory.scala
/XiangShan/src/main/scala/device/IMSICAsync.scala
/XiangShan/src/main/scala/device/MemEncrypt.scala
/XiangShan/src/main/scala/device/MemEncryptUtil.scala
/XiangShan/src/main/scala/device/RocketDebugWrapper.scala
/XiangShan/src/main/scala/device/imsic_axi_top.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/top/YamlParser.scala
LowPowerState.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/PMParameters.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRCustom.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/DretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MNretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/SretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSROoORead.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PFEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PMPEntryModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SstcInterruptGen.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/Trigger.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/cache/CacheConstants.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/BitmapCheck.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheCtrlUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/Bundles.scala
/XiangShan/src/main/scala/xiangshan/mem/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchInterface.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StreamPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/PrefetcherMonitor.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/main/scala/xiangshan/transforms/PrintModuleName.scala
/XiangShan/src/test/scala/top/SimTop.scala
/XiangShan/src/test/scala/xiangshan/frontend/FrontTrigger.scala
/XiangShan/utility
/XiangShan/yunsuan
8b33cd3013-Dec-2024 klin02 <[email protected]>

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
Wh

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
WhenContext. For example, when(cond1){XSDebug(cond2, pable)} to
XSDebug(cond1 && cond2, pable)

show more ...


/XiangShan/.github/filters.yaml
/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/format.yml
/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/openLLC
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/device/AXI4IntrGenerator.scala
/XiangShan/src/main/scala/device/AXI4SlaveModule.scala
/XiangShan/src/main/scala/device/TLTimer.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
DebugIdentityNode.scala
TLDump.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSDts.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2IqFpImp.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PMPEntryModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FpPipedFuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/BranchUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheTagTable.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/CompressUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Snapshot.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobDeqPtrWrapper.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/Interface.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/Trace.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/TraceBuffer.scala
/XiangShan/src/main/scala/xiangshan/cache/CacheConstants.scala
/XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/CtrlUnit.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AMOALU.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/FIFO.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/WaitTable.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/test/scala/top/SimTop.scala
/XiangShan/utility
/XiangShan/yunsuan
edb1dfaf27-Nov-2024 Haojin Tang <[email protected]>

chore: use scala-provided `distinctBy`


/XiangShan/.github/filters.yaml
/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/format.yml
/XiangShan/.github/workflows/perf.yml
/XiangShan/.gitignore
/XiangShan/.mill-version
/XiangShan/.scalafmt.conf
/XiangShan/Makefile
/XiangShan/README.md
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/images/xs-arch-kunminghu.svg
/XiangShan/openLLC
/XiangShan/readme.zh-cn.md
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/device/IMSIC.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDevice.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/top/XiangShanStage.scala
SeqUtils.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSDts.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/README.md
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/DretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MNretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/SretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryDEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CommitIDModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheTagModule.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/CompressUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Bim.scala
/XiangShan/src/main/scala/xiangshan/frontend/Composer.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/RAS.scala
/XiangShan/src/main/scala/xiangshan/frontend/README.md
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/FIFO.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/WaitTable.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/FDP.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/utility
/XiangShan/yunsuan
03df898a24-Oct-2024 zhangyuxin <[email protected]>

fix(utils): fix AXI4LiteBundle signal connection (#3779)

Reported-by: hong Zhao <[email protected]>
Fixed-by: jiuyue Ma <[email protected]>
Signed-off-by: yuxin Zhang <[email protected]>

Si

fix(utils): fix AXI4LiteBundle signal connection (#3779)

Reported-by: hong Zhao <[email protected]>
Fixed-by: jiuyue Ma <[email protected]>
Signed-off-by: yuxin Zhang <[email protected]>

Signed-off-by: yuxin Zhang <[email protected]>

show more ...


/XiangShan/.github/workflows/emu.yml
/XiangShan/Makefile
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/device/imsic_axi_top.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
AXI4Lite.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSDts.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/VecExcpDataMergeModule.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/ExceptionBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/ExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VfofBuffer.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/test/scala/top/SimMMIO.scala
/XiangShan/src/test/scala/top/SimTop.scala
/XiangShan/utility
44f2941b24-Sep-2024 Jiru Sun <[email protected]>

refactor(HPM): move HPMs from utils to utility repo (#3631)

Because HPMs will be used in Coupled L2 as well, delete
`PerfCounterUtils.scala` in Xiangshan and create
`HardwarePerfMonitor.scala` in

refactor(HPM): move HPMs from utils to utility repo (#3631)

Because HPMs will be used in Coupled L2 as well, delete
`PerfCounterUtils.scala` in Xiangshan and create
`HardwarePerfMonitor.scala` in Utility.
See also [Pull Request in
CoupledL2](https://github.com/OpenXiangShan/CoupledL2/pull/251#discussion_r1770738535).

show more ...


/XiangShan/.github/filters.yaml
/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/perf.yml
/XiangShan/Makefile
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/huancun
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/generate_all.sh
/XiangShan/scripts/parser.py
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/resources/aia
/XiangShan/src/main/scala/device/IMSICAsync.scala
/XiangShan/src/main/scala/device/RocketDebugWrapper.scala
/XiangShan/src/main/scala/device/imsic_axi_top.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDevice.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/DbEntry.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/PMParameters.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSDts.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/Og2ForVector.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/Instructions.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/DretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MNretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/SretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryDEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMNEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRFields.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapInstMod.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapTvalMod.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FliTable.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntFPToVec.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/BranchUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/AsynchronousMetaArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/storepipe/StorePipe.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchInterface.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StreamPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/PrefetcherMonitor.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/test/scala/top/SimMMIO.scala
/XiangShan/src/test/scala/xiangshan/backend/dispatch/Dispatch2IqMain.scala
/XiangShan/utility
/XiangShan/yunsuan
92c6103816-Aug-2024 Xuan Hu <[email protected]>

Frontend,Backend: add xxtvala support

* utils
* Add checkInputWidth function in NamedUInt to check if the UInt arg passed in has the same width as it defined.
* Frontend
* Pass the unexpanded in

Frontend,Backend: add xxtvala support

* utils
* Add checkInputWidth function in NamedUInt to check if the UInt arg passed in has the same width as it defined.
* Frontend
* Pass the unexpanded instruciton to IBuffer if the C extension 16 bits instruction is illegal.
* No need to use bypass illBuf, since the origin 16 bits instruction will be passed in the ctrlflow bundle.
* IBuffer
* Merge exceptionType and crossPageIPFFix into 3bit field, which type is IBufferExceptionType.
* IBufferExceptionType can hold illegal instruction exception.
* Backend
* CSROpType.ro is removed, since we can use rs1 and rd passed in imm field to distinguish CSRR and CSRW in CSR module.
* Create TrapInstMod to store the trap instruction and handle its update.

show more ...


/XiangShan/.github/workflows/check_verilog.py
/XiangShan/.github/workflows/emu.yml
/XiangShan/Makefile
/XiangShan/README.md
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/openLLC
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/resources/aia
/XiangShan/src/main/scala/device/AXI4Flash.scala
/XiangShan/src/main/scala/device/IMSIC.scala
/XiangShan/src/main/scala/device/IMSICAsync.scala
/XiangShan/src/main/scala/device/standalone/StandAloneCLINT.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala
/XiangShan/src/main/scala/device/standalone/StandAlonePLIC.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
NamedUInt.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/PipeGroupConnect.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataSource.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRCustom.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryDEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapInstMod.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/BranchUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/AgeDetector.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/RegCache.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheAgeTimer.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheDataModule.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheTagModule.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheTagTable.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/CompressUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/ExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/Interface.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/cache/wpu/VictimList.scala
/XiangShan/src/main/scala/xiangshan/cache/wpu/WPUWrapper.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/FreeList.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/utility
/XiangShan/yunsuan
e3da8bad22-Jul-2024 Tang Haojin <[email protected]>

build: purge chisel 3 and add deprecation check (#3250)


/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/nightly.yml
/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/macros/src/main/scala/CSRMacros.scala
/XiangShan/ready-to-run
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/resources/aia
/XiangShan/src/main/scala/device/IMSIC.scala
/XiangShan/src/main/scala/device/imsic_axi_top.scala
/XiangShan/src/main/scala/device/standalone/StandAloneCLINT.scala
/XiangShan/src/main/scala/device/standalone/standalone_device.mk
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Generator.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/top/XiangShanStage.scala
DebugMem.scala
MapUtils.scala
SeqUtils.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/PseudoInstruction.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAnnotation.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRCustom.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/DretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/SretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryDEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRFields.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRNamedConstant.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPMP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/ExceptionBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PMPEntryModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SstcInterruptGen.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/StateEnBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/Trigger.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala
/XiangShan/src/main/scala/xiangshan/backend/implicitCast.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/FIFO.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StreamPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/main/scala/xiangshan/transforms/Helpers.scala
/XiangShan/src/main/scala/xiangshan/transforms/NestedPrefixModulesAnnotation.scala
/XiangShan/src/main/scala/xiangshan/transforms/PrintControl.scala
/XiangShan/src/main/scala/xiangshan/transforms/PrintModuleName.scala
/XiangShan/src/test/scala/fu/IntDiv.scala
/XiangShan/src/test/scala/top/SimTop.scala
/XiangShan/src/test/scala/xiangshan/DecodeTest.scala
/XiangShan/src/test/scala/xiangshan/XSTester.scala
/XiangShan/src/test/scala/xiangshan/backend/BackendMain.scala
/XiangShan/yunsuan
bb2f3f5112-Jul-2024 Tang Haojin <[email protected]>

perf: use perfUtils in `Utility` (#3190)

Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies th

perf: use perfUtils in `Utility` (#3190)

Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies them and put them in Utility repository.

show more ...


/XiangShan/.github/workflows/emu.yml
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/huancun
/XiangShan/openLLC
/XiangShan/scripts/xiangshan.py
/XiangShan/src/chisel/main/scala/xiangshan/transforms/PrintModuleName.scala
/XiangShan/src/chisel3/main/scala/xiangshan/transforms/PrintModuleName.scala
/XiangShan/src/main/scala/device/AXI4Memory.scala
/XiangShan/src/main/scala/device/AXI4Plic.scala
/XiangShan/src/main/scala/device/TLTimer.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDevice.scala
/XiangShan/src/main/scala/device/standalone/standalone_device.mk
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/BusPerfMonitor.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
DebugIdentityNode.scala
PerfCounterUtils.scala
TLDump.scala
Trigger.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFReadArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2IqFpImp.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Bku.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Vsetu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/ByteMaskTailGen.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIDiv.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Snapshot.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobDeqPtrWrapper.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/storepipe/StorePipe.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/wpu/WPU.scala
/XiangShan/src/main/scala/xiangshan/cache/wpu/WPUWrapper.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/utility
/XiangShan/yunsuan
720dd62104-Jul-2024 Tang Haojin <[email protected]>

top: implement XSNoCTop and standalone devices (#3136)


/XiangShan/.github/workflows/check_verilog.py
/XiangShan/.github/workflows/emu.yml
/XiangShan/.gitmodules
/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/openLLC
/XiangShan/src/main/resources/aia
/XiangShan/src/main/scala/device/imsic_axi_top.scala
/XiangShan/src/main/scala/device/standalone/StandAloneCLINT.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDevice.scala
/XiangShan/src/main/scala/device/standalone/StandAlonePLIC.scala
/XiangShan/src/main/scala/device/standalone/standalone_device.mk
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/BusPerfMonitor.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
AXI4Lite.scala
VerilogAXI4LiteRecord.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/PipeGroupConnect.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Vsetu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/test/scala/top/SimTop.scala
/XiangShan/yunsuan
2993c5ec27-Jun-2024 Haojin Tang <[email protected]>

Top: use VerilogAXI4Record instead of `sed` to handle amba signal names


/XiangShan/.github/CODEOWNERS
/XiangShan/.github/ISSUE_TEMPLATE/1-bug_report.yml
/XiangShan/.github/ISSUE_TEMPLATE/2-feature_request.yaml
/XiangShan/.github/ISSUE_TEMPLATE/3-problem.yaml
/XiangShan/.github/ISSUE_TEMPLATE/4-other_question.yml
/XiangShan/.github/filters.yaml
/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/nightly.yml
/XiangShan/.mill-version
/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/huancun
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
VerilogAXI4Record.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/PipeGroupConnect.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataSource.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/Og2ForVector.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFReadArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFWBConflictChecker.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RdConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiterParams.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbFuBusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2IqFpImp.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Vsetu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntFPToVec.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/DivUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/MulUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIDiv.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/MultiWakeupQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/PregParams.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/ExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/cache/CacheInstruction.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/FakeDCache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/storepipe/StorePipe.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Composer.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/FIFO.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/FDP.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StreamPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/test/scala/top/SimTop.scala
/XiangShan/src/test/scala/xiangshan/XSTester.scala
/XiangShan/utility
/XiangShan/yunsuan
1e018fbf12-May-2024 Yinan Xu <[email protected]>

LogUtils: remove the unused reset condition (#2968)

Chisel Assertions are checked only when reset is deasserted.


/XiangShan/.github/workflows/check_verilog.py
/XiangShan/.github/workflows/nightly.yml
/XiangShan/.gitignore
/XiangShan/Makefile
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/ready-to-run
/XiangShan/src/main/scala/device/AXI4UART.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
LogUtils.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/DbEntry.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFReadArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFWBConflictChecker.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RdConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiterParams.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbFuBusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FpNonPipedFuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FpPipedFuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/FuBusyTableWrite.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/ImmExtractor.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/PregParams.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/FakeDCache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/storepipe/StorePipe.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/FDP.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StreamPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/PrefetcherMonitor.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/utility
/XiangShan/yunsuan
ec49b12719-Apr-2024 sinsanction <[email protected]>

Backend: reduce the width of LoadDependency to 2 bits

048165bd23-Apr-2024 Kamimiao <[email protected]>

Bump utility and difftest (#2901)

* fix nightly CI


/XiangShan/.github/workflows/nightly.yml
/XiangShan/difftest
/XiangShan/huancun
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataSource.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/Og2ForVector.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFWBConflictChecker.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/ByteMaskTailGen.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/ExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobDeqPtrWrapper.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobEnqPtrWrapper.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/test/scala/xiangshan/backend/fu/vector/ByteMaskTailGenTest.scala
/XiangShan/utility
55d7543520-Mar-2024 Tang Haojin <[email protected]>

ClockGate: remove `@*` after `always_latch`


/XiangShan/.github/workflows/emu.yml
/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/huancun
/XiangShan/ready-to-run
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/device/AXI4Memory.scala
/XiangShan/src/main/scala/device/AXI4UART.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Generator.scala
ClockGate.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSDts.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/LsInfo.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntFPToVec.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/Trigger.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecNonPipedFuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/FakeDCache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLBMissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TlbPrefetch.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StreamPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSFlowQueue.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/utility
/XiangShan/yunsuan
47e7896c28-Mar-2024 chengguanghui <[email protected]>

Trigger: optimize trigger

* delete data trigger in frontend

* optimiza trigger comparison logic
co-author-by: Guokai Chen <[email protected]>

* delete frontendTiming & frontendChain

Trigger: optimize trigger

* delete data trigger in frontend

* optimiza trigger comparison logic
co-author-by: Guokai Chen <[email protected]>

* delete frontendTiming & frontendChain in TriggerCf

show more ...

b9ef0a4218-Mar-2024 Xuan Hu <[email protected]>

Merge remote-tracking branch 'upstream/master' into tmp-backend-merge-fixtiming


/XiangShan/.github/ISSUE_TEMPLATE/1-bug_report.md
/XiangShan/.github/ISSUE_TEMPLATE/2-feature_request.md
/XiangShan/.github/ISSUE_TEMPLATE/3-problem.md
/XiangShan/.github/ISSUE_TEMPLATE/4-other_question.md
/XiangShan/.github/ISSUE_TEMPLATE/config.yml
/XiangShan/.github/workflows/emu.yml
/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/fudian
/XiangShan/huancun
/XiangShan/rocket-chip
/XiangShan/scripts/vlsi_mem_gen
/XiangShan/scripts/xiangshan.py
/XiangShan/src/chisel/main/scala/top/XiangShanStage.scala
/XiangShan/src/main/scala/device/AXI4Memory.scala
/XiangShan/src/main/scala/top/Configs.scala
Trigger.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/MemCtrl.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataSource.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFReadArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFWBConflictChecker.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/Instructions.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/BranchUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/AgeDetector.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/FuBusyTableWrite.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/ImmExtractor.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/NewAgeDetector.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/PregParams.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBankedArray.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/FreeList.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/DatamoduleResultBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/StorePrefetchBursts.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VLFlowQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VLUopQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSFlowQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSUopQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/utility
/XiangShan/yunsuan
5f4ac34118-Dec-2023 xiaofeibao-xjtu <[email protected]>

wakeup: remove flush between iq and wakeup queue

2aaa83c008-Dec-2023 xiaofeibao-xjtu <[email protected]>

backend: WBArbiter support two out at same time, fast wakeup remove valid

ec1fea8405-Dec-2023 zhanglyGit <[email protected]>

Backend: optimize wakeupQueue timing

0c7ebb5804-Dec-2023 xiaofeibao-xjtu <[email protected]>

WakeupQueue: pdest copy


/XiangShan/Makefile
PipeWithFlush.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WakeUpConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntFPToVec.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecNonPipedFuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIDiv.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/AgeDetector.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/CancelNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/FuBusyTableRead.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/FuBusyTableWrite.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/ImmExtractor.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/MultiWakeupQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/NewAgeDetector.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSFlowQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSUopQueue.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/test/scala/xiangshan/backend/issue/MultiWakeupQueueMain.scala
/XiangShan/src/test/scala/xiangshan/utils/GenPipeWithFlush.scala
/XiangShan/yunsuan
45f43e6e19-Jan-2024 Tang Haojin <[email protected]>

chore: bump chisel 6.0.0 (#2654)

BREAKING CHANGE: `SimTop.v` / `XSTop.v` now generated in `build/rtl`


/XiangShan/.github/workflows/emu.yml
/XiangShan/Makefile
/XiangShan/README.md
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/fudian
/XiangShan/huancun
/XiangShan/rocket-chip
/XiangShan/scripts/top-down/.gitignore
/XiangShan/scripts/top-down/README.md
/XiangShan/scripts/top-down/configs.py
/XiangShan/scripts/top-down/draw.py
/XiangShan/scripts/top-down/resources/spec06_rv64gcb_o2_20m.json
/XiangShan/scripts/top-down/top_down.py
/XiangShan/scripts/top-down/utils.py
/XiangShan/scripts/vlsi_mem_gen
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/device/AXI4DummySD.scala
/XiangShan/src/main/scala/device/AXI4Flash.scala
/XiangShan/src/main/scala/top/Configs.scala
Trigger.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Rs.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBankedArray.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/DatamoduleResultBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/StorePrefetchBursts.scala
/XiangShan/src/test/scala/top/SimTop.scala
/XiangShan/utility
dab1c36e11-Dec-2023 sinceforYy <[email protected]>

ClockGate: modify the latch to adapt to verilator 5.218


/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/difftest
/XiangShan/scripts/top-down/.gitignore
/XiangShan/scripts/top-down/README.md
/XiangShan/scripts/top-down/configs.py
/XiangShan/scripts/top-down/draw.py
/XiangShan/scripts/top-down/resources/spec06_rv64gcb_o2_20m.json
/XiangShan/scripts/top-down/top_down.py
/XiangShan/scripts/top-down/utils.py
/XiangShan/src/main/scala/device/AXI4DummySD.scala
/XiangShan/src/main/scala/device/AXI4Flash.scala
ClockGate.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/LsInfo.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/MemCtrl.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgtu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecNonPipedFuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VLFlowQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VLUopQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VLWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSFlowQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSUopQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/test/scala/top/SimTop.scala
/XiangShan/utility
/XiangShan/yunsuan
8241cb8517-Dec-2023 Xuan Hu <[email protected]>

Merge remote-tracking branch 'upstream/master' into backendq


/XiangShan/.github/CODEOWNERS
/XiangShan/.github/workflows/emu.yml
/XiangShan/Makefile
/XiangShan/README.md
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/huancun
/XiangShan/readme.zh-cn.md
/XiangShan/scripts/sram_size_collect.py
/XiangShan/scripts/xiangshan.py
/XiangShan/src/chisel/main/scala/top/XiangShanStage.scala
/XiangShan/src/chisel/main/scala/xiangshan/transforms/Helpers.scala
/XiangShan/src/chisel/main/scala/xiangshan/transforms/PrintControl.scala
/XiangShan/src/chisel/main/scala/xiangshan/transforms/PrintModuleName.scala
/XiangShan/src/chisel/main/scala/xiangshan/types.scala
/XiangShan/src/chisel/test/scala/xiangshan/types.scala
/XiangShan/src/chisel3/main/scala/top/XiangShanStage.scala
/XiangShan/src/chisel3/main/scala/xiangshan/transforms/PrintControl.scala
/XiangShan/src/chisel3/main/scala/xiangshan/transforms/PrintModuleName.scala
/XiangShan/src/chisel3/main/scala/xiangshan/types.scala
/XiangShan/src/chisel3/test/scala/xiangshan/types.scala
/XiangShan/src/main/scala/device/AXI4Memory.scala
/XiangShan/src/main/scala/device/AXI4RAM.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Generator.scala
/XiangShan/src/main/scala/top/Top.scala
PerfCounterUtils.scala
Trigger.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSDts.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Vsetu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToVec.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/FakeDCache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Composer.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBankedArray.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/main/scala/xiangshan/transforms/PrintControl.scala
/XiangShan/src/test/scala/fu/IntDiv.scala
/XiangShan/src/test/scala/top/SimTop.scala
/XiangShan/src/test/scala/xiangshan/DecodeTest.scala
/XiangShan/utility

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