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Searched defs:s2_valid (Results 1 – 14 of 14) sorted by relevance

/XiangShan/src/main/scala/xiangshan/mem/lsqueue/
H A DLoadExceptionBuffer.scala55 val s2_valid = (0 until enqPortNum).map(i => constant
H A DLoadQueueUncache.scala359 val s2_valid = (0 until LoadPipelineWidth).map(i => { constant
H A DStoreQueue.scala99 val s2_valid = (0 until enqPortNum).map(i => constant
/XiangShan/src/main/scala/xiangshan/cache/dcache/storepipe/
H A DStorePipe.scala149 val s2_valid = RegNext(s1_valid) && RegNext(!io.lsu.s1_kill) constant
/XiangShan/src/main/scala/xiangshan/mem/prefetch/
H A DL1StridePrefetcher.scala191 val s2_valid = GatedValidRegNext(s1_valid && s1_can_send_pf) constant
H A DL1StreamPrefetcher.scala325 val s2_valid = GatedValidRegNext(s1_valid) constant
H A DSMSPrefetcher.scala698 val s2_valid = GatedValidRegNext(s1_valid && !s1_wait, false.B) constant
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/
H A DMainPipe.scala108 val s2_valid = Bool() constant
397 val s2_valid = RegInit(false.B) constant
/XiangShan/src/main/scala/xiangshan/mem/pipeline/
H A DStoreUnit.scala429 val s2_valid = RegInit(false.B) constant
H A DHybridUnit.scala814 val s2_valid = RegInit(false.B) constant
H A DLoadUnit.scala1149 val s2_valid = RegInit(false.B) constant
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/
H A DLoadPipe.scala325 val s2_valid = RegInit(false.B) constant
/XiangShan/src/main/scala/xiangshan/cache/mmu/
H A DTLB.scala437 val s2_valid = portTranslateEnable(idx) && (onlyS2 || allS2xlate) constant
H A DMMUBundle.scala306 …val s2_valid = Mux(s2page_pageSuper, VecInit(Seq.fill(tlbcontiguous)(true.B)), VecInit(UIntToOH(it… constant