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Searched refs:init (Results 1 – 25 of 44) sorted by relevance

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/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/
H A DCSRFields.scala126 var init: Data = null variable
137 if (this.init != null && !factory.all.exists(_.litValue == this.init.litValue)) {
138 factory.asInstanceOf[CSREnum].addNewValue(init.asUInt)
175 def needReset: Boolean = init != null
182 protected def resetCheck[T <: EnumType](init: T): Unit = {
184 require(this.factory.all.contains(init),
187 | Please check if $init is the enum in the $factory")
193 protected def resetCheck(init: UInt): Unit = {
195 require(this.factory.all.exists(_.litValue == init.litValue),
211 def withReset[T <: EnumType](init: T): this.type = {
[all …]
H A DPMAEntryModule.scala32 pmaAddrInit.zip(pmaMaskInit).zip(pmaInit).foreach { case ((addr, mask), init) =>
33 addr := genAddr(init).U((PMPAddrWidth-PMPOffBits).W)
34 mask := genMask(init.a, genAddr(init))
149 def genAddr(init: PMAConfigEntry): BigInt = {
150 if (init.a < 2) {
151 shift_addr(init.base_addr)
153 get_napot(init.base_addr, init.range)
H A DCSRBundle.scala48 def init: this.type = { method
49 val init = Wire(this) constant
51 init.elements.foreach { case (str, field: CSREnumType) =>
52 field := (if (field.init != null) field.factory(field.init.asUInt) else field.factory(0.U))
55 init.asInstanceOf[this.type]
H A DUnprivileged.scala128 val VLENB = VlenbField(63, 0).withReset(VlenbField.init)
263 val init = Value((VLEN / 8).U) constant
H A DCSRModule.scala24 protected val reg = (if (bundle.needReset) RegInit(bundle, bundle.init) else Reg(bundle))
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/
H A DLsInfo.scala52 def init(implicit p: Parameters): DebugLsInfo = { method
112 def init(implicit p: Parameters): LsTopdownInfo = 0.U.asTypeOf(new LsTopdownInfo) method
H A DRedirectGenerator.scala85 …RegNext(s1_isReplay && s1_redirect_valid_reg && s1_redirect_bits_reg.flushItself(), init = false.B)
/XiangShan/src/test/scala/top/
H A DSimTop.scala114 Constantin.init(enableConstantin && !envInFPGA)
115 ChiselDB.init(enableChiselDB && !envInFPGA)
/XiangShan/src/main/scala/xiangshan/backend/fu/
H A DFuncUnit.scala172 …def pipelineReg(init: FuncUnitInput , valid:Bool, ready: Bool,latency: Int, flush:ValidIO[Redirect…
175 val ctrlVec = init.ctrl +: Seq.fill(latency)(Reg(chiselTypeOf(io.in.bits.ctrl)))
176 val dataVec = init.data +: Seq.fill(latency)(Reg(chiselTypeOf(io.in.bits.data)))
177 … val perfVec = init.perfDebugInfo +: Seq.fill(latency)(Reg(chiselTypeOf(io.in.bits.perfDebugInfo)))
178 … val seqNumVec = init.debug_seqNum +: Seq.fill(latency)(Reg(chiselTypeOf(io.in.bits.debug_seqNum)))
H A DPMP.scala303 init: () => (Vec[UInt], Vec[UInt], Vec[UInt]),
311 val init_value = init()
/XiangShan/src/main/scala/xiangshan/frontend/icache/
H A DIPrefetch.scala201 init = 0.U(PAddrBitsMax.W),
208 init = 0.U.asTypeOf(fromITLB(i).bits.isForVSnonLeafPTE),
215 init = 0.U(ExceptionType.width.W),
222 init = 0.U.asTypeOf(fromITLB(i).bits.pbmt(0)),
/XiangShan/src/main/scala/xiangshan/backend/fu/util/
H A DDebugCSR.scala44 def init: UInt = ( method
/XiangShan/src/main/scala/utils/
H A DArbiterHelper.scala28 case _ => true.B +: request.tail.init.scanLeft(request.head)(_ || _).map(!_)
/XiangShan/src/main/scala/xiangshan/frontend/
H A DFrontendBundle.scala200 val mapping = exceptions.init.map(e => (e =/= none) -> e)
562 def br_slot_valids = slot_valids.init
570 (br_slot_valids zip br_taken_mask.init).map { case (t, v) => t && v } :+ (
583 taken_mask_on_slot.map(_ && hit).init :+
625 !real_slot_taken_mask().init.reduce(_ || _) &&
H A DIFU.scala685 fromFtqRedirectReg.valid := RegNext(fromFtq.redirect.valid, init = false.B)
686 val mmioF3Flush = RegNext(f3_flush, init = false.B)
883 checkerIn.fire_in := RegNext(f2_fire, init = false.B)
1060 val wb_valid = RegNext(wb_enable, init = false.B)
1095 when(wb_valid && RegNext(f3_hasLastHalf, init = false.B)
1098 init = false.B
1104 when(wb_valid && RegNext(f3_hasLastHalf, init = false.B)
H A DITTAGE.scala473 val u_valid = RegNext(io.update.valid, init = false.B)
736 tables(i).io.update.valid := RegNext(updateMask(i), init = false.B)
737 tables(i).io.update.reset_u := RegNext(updateResetU, init = false.B)
H A DFauFTB.scala144 val u_valid = RegNext(io.update.valid, init = false.B)
/XiangShan/src/main/scala/device/
H A DAXI4IntrGenerator.scala64 w_fire = RegNext(w_fire, init=false.B)
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/
H A DAMOALU.scala47 val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_|_)
/XiangShan/scripts/
H A DconstantHelper.py93 self.init = random.randint(0, self.guide) if 'init' not in obj.keys() else obj['init']
332 const.append(constant.init)
/XiangShan/
H A Dreadme.zh-cn.md98 * 克隆本项目，运行 `make init` 以初始化本项目引用的开源子模块。
H A DREADME.md104 * Clone this project and run `make init` to initialize submodules.
/XiangShan/src/main/scala/xiangshan/cache/mmu/
H A DRepeater.scala80 assert(!RegNext(recv && io.ptw.resp.valid, init = false.B), "re-receive ptw.resp")
376 filter.map(_.ptw.resp.valid := GatedValidRegNext(io.ptw.resp.fire, init = false.B))
479 …val ptwResp_valid = GatedValidRegNext(io.ptw.resp.fire && Cat(ptwResp_OldMatchVec).orR, init = fal…
489 init = false.B)
/XiangShan/src/main/scala/xiangshan/backend/datapath/
H A DRFWBConflictChecker.scala49 case _ => request.head +: request.tail.init.scanLeft(request.head)(_ || _).map(!_)
/XiangShan/src/main/scala/top/
H A DTop.scala490 Constantin.init(enableConstantin && !envInFPGA)
491 ChiselDB.init(enableChiselDB && !envInFPGA)

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