configs, core: update some parameters (#1072)

* change ROB to 256 entries
* change physical register file to 192 entries
* re-organize reservation stations, function units and regfile

misc: code clean up (#1073)

* rename Roq to Rob

* remove trailing whitespaces

* remove unused parameters

Merge branch 'master' into me-opt

l2, core: add more performance counters (#942)

* Refactor print control transform

* Adda tilelink bus pmu

* Add performance counters for dispatch, issue, execute stages

* Add more counters

l2, core: add more performance counters (#942)

* Refactor print control transform

* Adda tilelink bus pmu

* Add performance counters for dispatch, issue, execute stages

* Add more counters in bus pmu

* Insert BusPMU between L3 and L2

* add some TMA perfcnt



Co-authored-by: LinJiawei <[email protected]>
Co-authored-by: William Wang <[email protected]>
Co-authored-by: wangkaifan <[email protected]>

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rename/roq/dispatch1: support EnableIntMoveElim=false
(finish refactoring) [TODO] remove useless code

backend, rename: support move elimination (#920)

* Bundle, Rename: Add some comments
FreeList, RenameTable: Comment out unused variables

* refcnt: Implement AdderTree for reference counter

*

backend, rename: support move elimination (#920)

* Bundle, Rename: Add some comments
FreeList, RenameTable: Comment out unused variables

* refcnt: Implement AdderTree for reference counter

* build.sc: add testOne method for unit test

* AdderTest: add testbench for Adder (passed)

* AdderTree: Add testbench for AdderTree (passed)

* ReferenceCounter: implement a 2-bit counter

* Rename: remove redundant code

* Rename: prepared for move elimination [WIP]

* Roq: add eliminated move bit in roq entry;
label elim move inst as writebacked
AlternativeFreeList: new impl for int free list
Rename: change io of free list
Dispatch1: (todo) not send move to intDq
Bundle: add eliminatedMove bit in roqCommitInfo, uop and debugio
ReferenceCounter: add debug print msg

* Dispatch1: [BUG FIX] not send move inst to IntDq

* DecodeUnit: [BUG FIX] differentiate li from mv

* Bug fix:
1. Dispatch1: should not label pdest of move as busy in busy table
2. Rename: use psrc0 to index bit vec isMax
3. AlternativeFreeList: fix maxVec calculation logic and ref counter
increment logic
Besides, more debug info and assertions were added.

* AlternativeFreeList Bug Fix:
1. add redirect input - shouldn't allocate reg when redirect is
valid
2. handle duplicate preg in roqCommits in int free list

* AlternativeFreeList: Fix value assignment race condition

* Rename: Fix value assignment race condition too

* RenameTable: refactor spec/arch table write process

* Roq: Fix debug_exuData of move(addi) instruction
(it was trash data before because move needn't enter exu)

* Rename: change intFreeList's redirect process
(by setting headPtr back) and flush process

* ME: microbench & coremark & linux-hello passed
1. DecodeUnit: treat `mv x,x` inst as non-move
2. AlternativeFreeList: handle duplicate walk req correctly
3. Roq: fix debug_exuData bug (make sure writeback that updates
debug_exuData happens before ME instruction in program order)

* AlternativeFreeList: License added
build.sc: remove unused config
Others: comments added

* package rename: remove unused modules

* Roq: Replace debug_prf with a cleaner fix method

* Disp1/AltFL/Rename: del unnecessary white spaces

* build.sc: change stack size
AlternativeFreeList: turn off assertions

* build.sc: change stack size for test

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core: add basic debug mode features (#918)

Basic features of debug mode are implemented.

* Rewrite CSR for debug mode
* Peripheral work for implementing debug module
* Added single step support

core: add basic debug mode features (#918)

Basic features of debug mode are implemented.

* Rewrite CSR for debug mode
* Peripheral work for implementing debug module
* Added single step support
* Use difftest with JTAG support

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backend: add ExuBlock to wrap execution units and RS (#903)

Backend --> ExuBlock --> FuBlock --> Exu --> Function Units
--> --> Scheduler --> RS

misc: update PCL information (#899)

XiangShan is jointly released by ICT and PCL.

scheduler: add support for parameterization via rs and dp ports (#882)

This commit adds support for a parameterized scheduler. A scheduler
can be parameterized via issue and dispatch ports.

Note

scheduler: add support for parameterization via rs and dp ports (#882)

This commit adds support for a parameterized scheduler. A scheduler
can be parameterized via issue and dispatch ports.

Note: other parameters have not been tested.

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backend: wrap all RS into a larger scheduler module (#880)

This commit adds an non-parameterized scheduler containing all reservation stations.
Now IntegerBlock, FloatBlock, MemBlock contain only f

backend: wrap all RS into a larger scheduler module (#880)

This commit adds an non-parameterized scheduler containing all reservation stations.
Now IntegerBlock, FloatBlock, MemBlock contain only function units.
The Schduler connects dispatch with all function units.
Parameterization to be added later.

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backend: optimize dispatch and issue timing (#821)

* better select policy timing
* unified RS enqueue ports for 4 ALUs
* wrap imm extractor into a module
* backend,rs: wrap dataArray in RawDataMo

backend: optimize dispatch and issue timing (#821)

* better select policy timing
* unified RS enqueue ports for 4 ALUs
* wrap imm extractor into a module
* backend,rs: wrap dataArray in RawDataModuleTemplate
* should only bypass data between the same addr when allocate.valid

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Add MulanPSL-2.0 License (#824)

In this commit, we add License for XiangShan project.

backend,mem: add Store Sets memory dependence predictor (#796)

* LoadQueue: send stFtqIdx via rollback request

* It will make it possible for setore set to update its SSIT

* StoreSet: setup st

backend,mem: add Store Sets memory dependence predictor (#796)

* LoadQueue: send stFtqIdx via rollback request

* It will make it possible for setore set to update its SSIT

* StoreSet: setup store set update req

* StoreSet: add store set identifier table (SSIT)

* StoreSet: add last fetched store table (LFST)

* StoreSet: put SSIT into decode stage

* StoreSet: put LFST into dispatch1

* Future work: optimize timing

* RS: store rs now supports delayed issue

* StoreSet: add perf counter

* StoreSet: fix SSIT update logic

* StoreSet: delay LFST update input for 1 cycle

* StoreSet: fix LFST update logic

* StoreSet: fix LFST raddr width

* StoreSet: do not force store in ss issue in order

Classic store set requires store in the same store set issue in seq.
However, in current micro-architecture, such restrict will lead to
severe perf lost. We choose to disable it until we find another way
to fix it.

* StoreSet: support ooo store in the same store set

* StoreSet: fix store set merge logic

* StoreSet: check earlier store when read LFST

* If store-load pair is in the same dispatch bundle, loadWaitBit should
also be set for load

* StoreSet: increase default SSIT flush period

* StoreSet: fix LFST read logic

* Fix commit c0e541d14

* StoreSet: add StoreSetEnable parameter

* RSFeedback: add source type

* StoreQueue: split store addr and store data

* StoreQueue: update ls forward logic

* Now it supports splited addr and data

* Chore: force assign name for load/store unit

* RS: add rs'support for store a-d split

* StoreQueue: fix stlf logic

* StoreQueue: fix addr wb sq update logic

* AtomicsUnit: support splited a/d

* Parameters: disable store set by default

* WaitTable: wait table will not cause store delay

* WaitTable: recover default reset period to 2^17

* Fix dev-stad merge conflict

* StoreSet: enable storeset

* RS: disable store rs delay logic

CI perf shows that current delay logic will cause perf loss. Disable
unnecessary delay logic will help.

To be more specific, `io.readyVec` caused the problem. It will be
updated in future commits.

* RS: opt select logic with load delay (ldWait)

* StoreSet: disable 2-bit lwt

Co-authored-by: ZhangZifei <[email protected]>

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bundle: use Vec for src in ExuInput (#805)

This commit replaces src1, src2, src3 in Bundle ExuInput with Vec(3, UInt).
Should be easier for RS.

dispatch1: allow enq.ready when !enq.valid (#799)

DispatchQueue: wrap around tailPtr index when redirect (#800)

This commit fixes the bug when redirect.valid and the last valid instruction is in the last slot.
Previously the tailPtr becomes size.U

DispatchQueue: wrap around tailPtr index when redirect (#800)

This commit fixes the bug when redirect.valid and the last valid instruction is in the last slot.
Previously the tailPtr becomes size.U when there're no instructions before headPtr. It works fine
when DispatchQueueSize is power2.

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bundle,uop: use Vec for lsrc, psrc, srcState and srcType (#797)

This commit uses Vec for lsrc, psrc, srcState and srcType in MicroOp bundle.
This makes uop easier to access.

dispatch2: add detailed histogram counters for int/fp/ls regfile ports (#788)

Add dispatch and issue performance counters (#770)

In this commit, we add performance counters for dispatch and issue stages
to track the number of instructions dispatched and issued. Active regfil

Add dispatch and issue performance counters (#770)

In this commit, we add performance counters for dispatch and issue stages
to track the number of instructions dispatched and issued. Active regfile
read ports are counted as ready instruction source registers.

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Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's

Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr.
(2) DPI-C is cross-platform (Verilator, VCS, ...)
(3) difftest APIs are splited from emu.cpp to possibly support more backend platforms
(NEMU, Spike, ...)

The performance at this commit is quite slower than the original emu.
Performance issues will be fixed later.

* [WIP] SimTop: try to use 'XSTop' as soc

* CircularQueuePtr: ues F-bounded polymorphis instead implict helper

* Refactor parameters & Clean up code

* difftest: support basic difftest

* Support diffetst in new sim top

* Difftest; convert recode fmt to ieee754 when comparing fp regs

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Debug: add int/exc inst wb to debug queue

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Difftest: fix naive commit num limit

Co-authored-by: Yinan Xu <[email protected]>
Co-authored-by: William Wang <[email protected]>

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CircularQueuePtr: use F-bounded polymorphism instead of implicit helper (#750)

Add some in-core hardware performance counters (#731)

* csr: remove unused input perfcnt io

* perfcnt: add some in-core hardware performance counters

* perfcnt: optimize timing for hardware pe

Add some in-core hardware performance counters (#731)

* csr: remove unused input perfcnt io

* perfcnt: add some in-core hardware performance counters

* perfcnt: optimize timing for hardware performance counters

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Merge branch 'master' of github.com:RISCVERS/XiangShan

Refactor XSPerf, now we have three XSPerf Functions.
XSPerfAccumulate: sum up performance values.
XSPerfHistogram: count the occurrence of performance values, split them
into bins, so that we can est

Refactor XSPerf, now we have three XSPerf Functions.
XSPerfAccumulate: sum up performance values.
XSPerfHistogram: count the occurrence of performance values, split them
into bins, so that we can estimate their distribution.
XSPerfMax: get max of performance values.

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