debug - OpenGrok history log for /XiangShan/debug

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
214933ef	21-Feb-2023	bugGenerator <[email protected]>	bump difftest & mkdir for wave/perf for local-ci script's run-mode (#1927) * bump difftest, assign empty value to OBJCACHE * local-ci: mkdir for wave/perf at run-mode /XiangShan/.github/workflows/nightly.yml local_ci.py /XiangShan/difftest
9473e04d	20-Feb-2023	bugGenerator <[email protected]>	debug: add local-ci.py to run github/emy.yml's ci tests at local server (#1925) Usage: 1. run ci test `python3 scripts/local_ci.py --xs-path $(pwd) --run` 2. print ci test name `python3 script debug: add local-ci.py to run github/emy.yml's ci tests at local server (#1925) Usage: 1. run ci test `python3 scripts/local_ci.py --xs-path $(pwd) --run` 2. print ci test name `python3 scripts/local_ci.py --xs-path $(pwd) --show-test` 3. print ci test command into splited sh files. Run the sh manualy. `python3 scripts/local_ci.py --xs-path $(pwd)` More Params: --sh-path: default is xs-path/ci-sh. Other Params: --pick-test MC: only run 'EMU - MC' --numa: use numa ctrl, require eypc --head-sha: magic word, default is today's date --nemu-home/--am-home: don't know if it is used show more ... /XiangShan/.github/ISSUE_TEMPLATE/bug_report.md /XiangShan/.github/ISSUE_TEMPLATE/feature_request.md /XiangShan/.github/workflows/check_verilog.py /XiangShan/.github/workflows/emu.yml /XiangShan/.github/workflows/nightly.yml /XiangShan/.gitignore /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/Makefile.test /XiangShan/README.md /XiangShan/build.sc local_ci.py /XiangShan/difftest /XiangShan/fudian /XiangShan/huancun /XiangShan/images/wechat.png /XiangShan/images/xs-arch-nanhu.svg /XiangShan/images/xs-arch-yanqihu.svg /XiangShan/readme.zh-cn.md /XiangShan/ready-to-run /XiangShan/rocket-chip /XiangShan/scripts/constantHelper.py /XiangShan/scripts/top-down/.gitignore /XiangShan/scripts/top-down/README.md /XiangShan/scripts/top-down/file.f /XiangShan/scripts/top-down/json2f.py /XiangShan/scripts/top-down/run_emu.sh /XiangShan/scripts/top-down/top-down.sh /XiangShan/scripts/top-down/top_down.py /XiangShan/scripts/top-down/xsrun /XiangShan/scripts/utils/convert.sh /XiangShan/scripts/utils/convert_dir.sh /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/device/AXI4IntrGenerator.scala /XiangShan/src/main/scala/device/AXI4Keyboard.scala /XiangShan/src/main/scala/device/AXI4Memory.scala /XiangShan/src/main/scala/device/AXI4Plic.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4SlaveModule.scala /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/AXI4VGA.scala /XiangShan/src/main/scala/device/RocketDebugWrapper.scala /XiangShan/src/main/scala/device/TLPMA/TLPMA.scala /XiangShan/src/main/scala/gpu/GPU.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/BusPerfMonitor.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Generator.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/OverrideableQueue.scala /XiangShan/src/main/scala/utils/PerfCounterUtils.scala /XiangShan/src/main/scala/utils/Trigger.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/PMParameters.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSDts.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FUBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Rs.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/IndexMapping.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Bku.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/InputBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CryptoUtils.scala /XiangShan/src/main/scala/xiangshan/backend/issue/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/PayloadArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SelectPolicy.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/WakeupQueue.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/RefCounter.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/CacheConstants.scala /XiangShan/src/main/scala/xiangshan/cache/CacheInstruction.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWPU.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/FakeDCache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AMOALU.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/RefillPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/AsynchronousMetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLBMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TlbPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/Prefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/StreamPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Composer.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheProbeUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ReleaseUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ReplacePipe.scala /XiangShan/src/main/scala/xiangshan/mem/MaskedDataModule.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/MemTrace.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/WaitTable.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchInterface.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/DatamoduleResultBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/DummyVLSQ.scala /XiangShan/src/main/scala/xiangshan/mem/vector/MemVectorInterface.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xstransforms/PrintControl.scala /XiangShan/src/main/scala/xstransforms/PrintModuleName.scala /XiangShan/src/test/scala/fu/IntDiv.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/src/test/scala/xiangshan/DecodeTest.scala /XiangShan/src/test/scala/xiangshan/XSTester.scala /XiangShan/utility
a58e3351	23-Sep-2021	Li Qianruo <[email protected]>	Integer SRT16 Divider (#1019) * New SRT4 divider that may improve timing See "Digital reurrence dividers with reduced logical depth" * SRT16 Int Divider that is working properly * Fix bug r Integer SRT16 Divider (#1019) * New SRT4 divider that may improve timing See "Digital reurrence dividers with reduced logical depth" * SRT16 Int Divider that is working properly * Fix bug related to div 1 * Timing improved version of SRT16 int divider * Add copyright and made some minor changes * Fix bugs related to div 0 * Fix another div 0 bug * Fix another special case bug show more ... /XiangShan/.github/workflows/emu.yml /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/build.sc Makefile /XiangShan/difftest /XiangShan/fudian /XiangShan/huancun /XiangShan/ready-to-run /XiangShan/rocket-chip /XiangShan/scripts/utils/convert.sh /XiangShan/scripts/utils/convert_dir.sh /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4VGA.scala /XiangShan/src/main/scala/device/RocketDebugWrapper.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/BusPerfMonitor.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/DataModuleTemplate.scala /XiangShan/src/main/scala/utils/Hold.scala /XiangShan/src/main/scala/utils/Misc.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/PMA.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSDts.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FUBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Instructions.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/predecode/predecode.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Bmu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/InputBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/issue/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/PayloadArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SelectPolicy.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/FreeListBaseIO.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/MEFreeListIO.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/ICache.scala /XiangShan/src/main/scala/xiangshan/cache/ICacheMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/InstrUncache.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/L1plusCache.scala /XiangShan/src/main/scala/xiangshan/cache/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/BTLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLBMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PTW.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/L1plusPrefetcher.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Composer.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/local.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/MemUtils.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/fu/IntDiv.scala /XiangShan/src/test/scala/top/SimTop.scala
a3e87608	28-Jul-2021	William Wang <[email protected]>	Update difftest to use NEMU master branch (#902) misc: implement difftest as a submodule /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/build.sc Makefile /XiangShan/difftest /XiangShan/ready-to-run /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/SimTop.scala
f320e0f0	24-Jul-2021	Yinan Xu <[email protected]>	misc: update PCL information (#899) XiangShan is jointly released by ICT and PCL. /XiangShan/.gitignore /XiangShan/.gitmodules /XiangShan/.mill-version /XiangShan/Makefile /XiangShan/README.md /XiangShan/build.sbt /XiangShan/build.sc Makefile cputest.sh env.sh perf_sbuffer.sh sc_stat.sh /XiangShan/readme.zh-cn.md /XiangShan/ready-to-run /XiangShan/scripts/autorun/common/local_config.py /XiangShan/scripts/autorun/common/simulator_task_goback.py /XiangShan/scripts/autorun/common/task_tree_go_back.py /XiangShan/scripts/autorun/config.py /XiangShan/scripts/autorun/run.py /XiangShan/scripts/coverage/coverage.py /XiangShan/scripts/coverage/statistics.py /XiangShan/scripts/statistics.py /XiangShan/scripts/utils/lock-emu.c /XiangShan/scripts/xiangshan.py /XiangShan/src/main/resources/vsrc/regfile_160x64_10w16r_sim.v /XiangShan/src/main/scala/bus/tilelink/Arbiter.scala /XiangShan/src/main/scala/bus/tilelink/Metadata.scala /XiangShan/src/main/scala/bus/tilelink/TLUtilities.scala /XiangShan/src/main/scala/bus/tilelink/TileLink.scala /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/device/AXI4IntrGenerator.scala /XiangShan/src/main/scala/device/AXI4Keyboard.scala /XiangShan/src/main/scala/device/AXI4Plic.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4SlaveModule.scala /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/AXI4VGA.scala /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/difftest/Difftest.scala /XiangShan/src/main/scala/gpu/GPU.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/CircularQueuePtr.scala /XiangShan/src/main/scala/utils/DataDontCareNode.scala /XiangShan/src/main/scala/utils/DataModuleTemplate.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/ECC.scala /XiangShan/src/main/scala/utils/ExcitingUtils.scala /XiangShan/src/main/scala/utils/ExtractVerilogModules.scala /XiangShan/src/main/scala/utils/FlushableQueue.scala /XiangShan/src/main/scala/utils/GTimer.scala /XiangShan/src/main/scala/utils/Hold.scala /XiangShan/src/main/scala/utils/LFSR64.scala /XiangShan/src/main/scala/utils/LatencyPipe.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/LookupTree.scala /XiangShan/src/main/scala/utils/MIMOQueue.scala /XiangShan/src/main/scala/utils/Misc.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/utils/PerfCounterUtils.scala /XiangShan/src/main/scala/utils/PipelineConnect.scala /XiangShan/src/main/scala/utils/PriorityMuxDefault.scala /XiangShan/src/main/scala/utils/PriorityMuxGen.scala /XiangShan/src/main/scala/utils/RegMap.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/utils/ResetGen.scala /XiangShan/src/main/scala/utils/SRAMTemplate.scala /XiangShan/src/main/scala/utils/StopWatch.scala /XiangShan/src/main/scala/utils/TLDump.scala /XiangShan/src/main/scala/utils/TLIgnoreNode.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/PMA.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSDts.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FloatBlock.scala /XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Instructions.scala /XiangShan/src/main/scala/xiangshan/backend/decode/StoreSet.scala /XiangShan/src/main/scala/xiangshan/backend/decode/WaitTable.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/predecode/predecode.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/IndexMapping.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wb.scala /XiangShan/src/main/scala/xiangshan/backend/ftq/Ftq.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/issue/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/PayloadArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SelectPolicy.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/WakeupQueue.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/AMOALU.scala /XiangShan/src/main/scala/xiangshan/cache/AtomicsReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/DCache.scala /XiangShan/src/main/scala/xiangshan/cache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/ICache.scala /XiangShan/src/main/scala/xiangshan/cache/ICacheMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/InstrUncache.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/L1plusCache.scala /XiangShan/src/main/scala/xiangshan/cache/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/Mem.scala /XiangShan/src/main/scala/xiangshan/cache/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/Probe.scala /XiangShan/src/main/scala/xiangshan/cache/StoreReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/Uncache.scala /XiangShan/src/main/scala/xiangshan/cache/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLBMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PTW.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/L1plusPrefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/L2Prefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/Prefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/StreamPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/MaskedDataModule.scala /XiangShan/src/main/scala/xiangshan/mem/MemUtils.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xstransforms/PrintControl.scala /XiangShan/src/main/scala/xstransforms/PrintModuleName.scala /XiangShan/src/test/csrc/common/axi4.cpp /XiangShan/src/test/csrc/common/axi4.h /XiangShan/src/test/csrc/common/common.cpp /XiangShan/src/test/csrc/common/common.h /XiangShan/src/test/csrc/common/compress.cpp /XiangShan/src/test/csrc/common/compress.h /XiangShan/src/test/csrc/common/device.cpp /XiangShan/src/test/csrc/common/device.h /XiangShan/src/test/csrc/common/flash.cpp /XiangShan/src/test/csrc/common/flash.h /XiangShan/src/test/csrc/common/keyboard.cpp /XiangShan/src/test/csrc/common/macro.h /XiangShan/src/test/csrc/common/ram.cpp /XiangShan/src/test/csrc/common/ram.h /XiangShan/src/test/csrc/common/sdcard.cpp /XiangShan/src/test/csrc/common/sdcard.h /XiangShan/src/test/csrc/common/uart.cpp /XiangShan/src/test/csrc/common/vga.cpp /XiangShan/src/test/csrc/difftest/difftest.cpp /XiangShan/src/test/csrc/difftest/difftest.h /XiangShan/src/test/csrc/difftest/goldenmem.cpp /XiangShan/src/test/csrc/difftest/goldenmem.h /XiangShan/src/test/csrc/difftest/interface.cpp /XiangShan/src/test/csrc/difftest/interface.h /XiangShan/src/test/csrc/difftest/nemuproxy.cpp /XiangShan/src/test/csrc/difftest/nemuproxy.h /XiangShan/src/test/csrc/difftest/ref.cpp /XiangShan/src/test/csrc/difftest/ref.h /XiangShan/src/test/csrc/vcs/main.cpp /XiangShan/src/test/csrc/verilator/emu.cpp /XiangShan/src/test/csrc/verilator/emu.h /XiangShan/src/test/csrc/verilator/main.cpp /XiangShan/src/test/csrc/verilator/snapshot.cpp /XiangShan/src/test/csrc/verilator/snapshot.h /XiangShan/src/test/scala/cache/CacheTest.scala /XiangShan/src/test/scala/cache/L1DTest/CoreAgent.scala /XiangShan/src/test/scala/cache/L1DTest/CoreTransatcion.scala /XiangShan/src/test/scala/cache/L1DTest/L1DTest.scala /XiangShan/src/test/scala/cache/L1plusCacheTest.scala /XiangShan/src/test/scala/cache/L2CacheNonInclusiveGetTest.scala /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/cache/ReplaceTest.scala /XiangShan/src/test/scala/cache/TLCTest/BigIntUtil.scala /XiangShan/src/test/scala/cache/TLCTest/FixedBlockFuzzer.scala /XiangShan/src/test/scala/cache/TLCTest/TLCAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTest.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTransaction.scala /XiangShan/src/test/scala/cache/TLCTest/TLMasterMMIO.scala /XiangShan/src/test/scala/cache/TLCTest/TLSlaveMMIO.scala /XiangShan/src/test/scala/cache/TLCTest/TLULAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLULMMIO.scala /XiangShan/src/test/scala/cache/UnalignedGetTest.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala /XiangShan/src/test/scala/xiangshan/testutils/PartialDecoupledDriver.scala /XiangShan/src/test/scala/xiangshan/testutils/TestCaseGenerator.scala /XiangShan/src/test/testcase/Makefile /XiangShan/src/test/testcase/tests/double-loop.c /XiangShan/src/test/testcase/tests/nested-loop.c /XiangShan/src/test/vsrc/common/assert.v /XiangShan/src/test/vsrc/common/difftest.v /XiangShan/src/test/vsrc/common/ram.v /XiangShan/src/test/vsrc/common/ref.v /XiangShan/src/test/vsrc/vcs/top.v /XiangShan/tools/readmemh/Makefile /XiangShan/tools/readmemh/gen-treadle-readmemh.c /XiangShan/tools/readmemh/groupby-4byte.c /XiangShan/tools/readmemh/split-readmemh.c /XiangShan/vcs.mk /XiangShan/verilator.mk /XiangShan/xs-arch-simple.svg
c6d43980	04-Jun-2021	Lemover <[email protected]>	Add MulanPSL-2.0 License (#824) In this commit, we add License for XiangShan project. /XiangShan/.github/workflows/emu.yml /XiangShan/.gitignore /XiangShan/.mill-version /XiangShan/LICENSE /XiangShan/Makefile /XiangShan/README.md /XiangShan/berkeley-hardfloat /XiangShan/block-inclusivecache-sifive /XiangShan/build.sc Makefile cputest.sh env.sh perf_sbuffer.sh sc_stat.sh /XiangShan/rocket-chip /XiangShan/scripts/autorun/common/local_config.py /XiangShan/scripts/autorun/common/simulator_task_goback.py /XiangShan/scripts/autorun/common/task_tree_go_back.py /XiangShan/scripts/autorun/config.py /XiangShan/scripts/autorun/run.py /XiangShan/scripts/coverage/coverage.py /XiangShan/scripts/coverage/statistics.py /XiangShan/scripts/statistics.py /XiangShan/scripts/utils/lock-emu.c /XiangShan/scripts/vlsi_mem_gen /XiangShan/scripts/xiangshan.py /XiangShan/src/main/resources/vsrc/regfile_160x64_10w16r_sim.v /XiangShan/src/main/scala/bus/tilelink/Arbiter.scala /XiangShan/src/main/scala/bus/tilelink/Metadata.scala /XiangShan/src/main/scala/bus/tilelink/TLUtilities.scala /XiangShan/src/main/scala/bus/tilelink/TileLink.scala /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/device/AXI4IntrGenerator.scala /XiangShan/src/main/scala/device/AXI4Keyboard.scala /XiangShan/src/main/scala/device/AXI4Plic.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4SlaveModule.scala /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/AXI4VGA.scala /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/difftest/Difftest.scala /XiangShan/src/main/scala/gpu/GPU.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/CircularQueuePtr.scala /XiangShan/src/main/scala/utils/DataDontCareNode.scala /XiangShan/src/main/scala/utils/DataModuleTemplate.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/ECC.scala /XiangShan/src/main/scala/utils/ExcitingUtils.scala /XiangShan/src/main/scala/utils/ExtractVerilogModules.scala /XiangShan/src/main/scala/utils/FlushableQueue.scala /XiangShan/src/main/scala/utils/GTimer.scala /XiangShan/src/main/scala/utils/Hold.scala /XiangShan/src/main/scala/utils/LFSR64.scala /XiangShan/src/main/scala/utils/LatencyPipe.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/LookupTree.scala /XiangShan/src/main/scala/utils/MIMOQueue.scala /XiangShan/src/main/scala/utils/Misc.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/utils/PerfCounterUtils.scala /XiangShan/src/main/scala/utils/PipelineConnect.scala /XiangShan/src/main/scala/utils/PriorityMuxDefault.scala /XiangShan/src/main/scala/utils/PriorityMuxGen.scala /XiangShan/src/main/scala/utils/RegMap.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/utils/ResetGen.scala /XiangShan/src/main/scala/utils/SRAMTemplate.scala /XiangShan/src/main/scala/utils/StopWatch.scala /XiangShan/src/main/scala/utils/TLDump.scala /XiangShan/src/main/scala/utils/TLIgnoreNode.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/PMA.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSDts.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FloatBlock.scala /XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Instructions.scala /XiangShan/src/main/scala/xiangshan/backend/decode/StoreSet.scala /XiangShan/src/main/scala/xiangshan/backend/decode/WaitTable.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/predecode/predecode.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/IndexMapping.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wb.scala /XiangShan/src/main/scala/xiangshan/backend/ftq/Ftq.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/issue/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/PayloadArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SelectPolicy.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/WakeupQueue.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/AMOALU.scala /XiangShan/src/main/scala/xiangshan/cache/AtomicsReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/DCache.scala /XiangShan/src/main/scala/xiangshan/cache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/ICache.scala /XiangShan/src/main/scala/xiangshan/cache/ICacheMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/InstrUncache.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/L1plusCache.scala /XiangShan/src/main/scala/xiangshan/cache/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/Mem.scala /XiangShan/src/main/scala/xiangshan/cache/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/PTW.scala /XiangShan/src/main/scala/xiangshan/cache/Probe.scala /XiangShan/src/main/scala/xiangshan/cache/StoreReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/Uncache.scala /XiangShan/src/main/scala/xiangshan/cache/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/L1plusPrefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/L2Prefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/Prefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/StreamPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/MaskedDataModule.scala /XiangShan/src/main/scala/xiangshan/mem/MemUtils.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xstransforms/PrintModuleName.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/csrc/common/axi4.cpp /XiangShan/src/test/csrc/common/axi4.h /XiangShan/src/test/csrc/common/common.cpp /XiangShan/src/test/csrc/common/common.h /XiangShan/src/test/csrc/common/compress.cpp /XiangShan/src/test/csrc/common/compress.h /XiangShan/src/test/csrc/common/device.cpp /XiangShan/src/test/csrc/common/device.h /XiangShan/src/test/csrc/common/flash.cpp /XiangShan/src/test/csrc/common/flash.h /XiangShan/src/test/csrc/common/keyboard.cpp /XiangShan/src/test/csrc/common/macro.h /XiangShan/src/test/csrc/common/ram.cpp /XiangShan/src/test/csrc/common/ram.h /XiangShan/src/test/csrc/common/sdcard.cpp /XiangShan/src/test/csrc/common/sdcard.h /XiangShan/src/test/csrc/common/uart.cpp /XiangShan/src/test/csrc/common/vga.cpp /XiangShan/src/test/csrc/difftest/difftest.cpp /XiangShan/src/test/csrc/difftest/difftest.h /XiangShan/src/test/csrc/difftest/goldenmem.cpp /XiangShan/src/test/csrc/difftest/goldenmem.h /XiangShan/src/test/csrc/difftest/interface.cpp /XiangShan/src/test/csrc/difftest/interface.h /XiangShan/src/test/csrc/difftest/nemuproxy.cpp /XiangShan/src/test/csrc/difftest/nemuproxy.h /XiangShan/src/test/csrc/difftest/ref.cpp /XiangShan/src/test/csrc/difftest/ref.h /XiangShan/src/test/csrc/vcs/main.cpp /XiangShan/src/test/csrc/verilator/emu.cpp /XiangShan/src/test/csrc/verilator/emu.h /XiangShan/src/test/csrc/verilator/main.cpp /XiangShan/src/test/csrc/verilator/snapshot.cpp /XiangShan/src/test/csrc/verilator/snapshot.h /XiangShan/src/test/scala/cache/CacheTest.scala /XiangShan/src/test/scala/cache/L1DTest/CoreAgent.scala /XiangShan/src/test/scala/cache/L1DTest/CoreTransatcion.scala /XiangShan/src/test/scala/cache/L1DTest/L1DTest.scala /XiangShan/src/test/scala/cache/L1plusCacheTest.scala /XiangShan/src/test/scala/cache/L2CacheNonInclusiveGetTest.scala /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/cache/ReplaceTest.scala /XiangShan/src/test/scala/cache/TLCTest/BigIntUtil.scala /XiangShan/src/test/scala/cache/TLCTest/FixedBlockFuzzer.scala /XiangShan/src/test/scala/cache/TLCTest/TLCAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTest.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTransaction.scala /XiangShan/src/test/scala/cache/TLCTest/TLMasterMMIO.scala /XiangShan/src/test/scala/cache/TLCTest/TLSlaveMMIO.scala /XiangShan/src/test/scala/cache/TLCTest/TLULAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLULMMIO.scala /XiangShan/src/test/scala/cache/UnalignedGetTest.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala /XiangShan/src/test/scala/xiangshan/testutils/PartialDecoupledDriver.scala /XiangShan/src/test/scala/xiangshan/testutils/TestCaseGenerator.scala /XiangShan/src/test/testcase/Makefile /XiangShan/src/test/testcase/tests/double-loop.c /XiangShan/src/test/testcase/tests/nested-loop.c /XiangShan/src/test/vsrc/common/assert.v /XiangShan/src/test/vsrc/common/difftest.v /XiangShan/src/test/vsrc/common/ram.v /XiangShan/src/test/vsrc/common/ref.v /XiangShan/src/test/vsrc/vcs/top.v /XiangShan/tools/readmemh/Makefile /XiangShan/tools/readmemh/gen-treadle-readmemh.c /XiangShan/tools/readmemh/groupby-4byte.c /XiangShan/tools/readmemh/split-readmemh.c /XiangShan/vcs.mk /XiangShan/verilator.mk
53c7ab8b	01-Feb-2021	William Wang <[email protected]>	Merge remote-tracking branch 'origin/master' into mem-timing /XiangShan/block-inclusivecache-sifive Makefile /XiangShan/src/main/scala/top/Parameters.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FloatBlock.scala /XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/ftq/Ftq.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/AtomicsReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/DCache.scala /XiangShan/src/main/scala/xiangshan/cache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/Probe.scala /XiangShan/src/main/scala/xiangshan/cache/StoreReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/tlb.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/scala/cache/L1DTest/CoreAgent.scala /XiangShan/src/test/scala/cache/L1DTest/CoreTransatcion.scala /XiangShan/src/test/scala/cache/L1DTest/L1DTest.scala /XiangShan/src/test/scala/cache/L1plusCacheTest.scala /XiangShan/src/test/scala/cache/L2CacheNonInclusiveGetTest.scala /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/cache/TLCTest/BigIntUtil.scala /XiangShan/src/test/scala/cache/TLCTest/FixedBlockFuzzer.scala /XiangShan/src/test/scala/cache/TLCTest/TLCAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTest.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTransaction.scala /XiangShan/src/test/scala/cache/TLCTest/TLMasterMMIO.scala /XiangShan/src/test/scala/cache/TLCTest/TLSlaveMMIO.scala /XiangShan/src/test/scala/cache/TLCTest/TLULAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLULMMIO.scala /XiangShan/src/test/scala/cache/UnalignedGetTest.scala /XiangShan/src/test/scala/xiangshan/frontend/RASTest.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala /XiangShan/src/test/scala/xiangshan/memend/SbufferTest.scala
3802dba5	01-Feb-2021	William Wang <[email protected]>	chore: update debug script /XiangShan/.gitignore /XiangShan/Makefile /XiangShan/block-inclusivecache-sifive Makefile /XiangShan/scripts/vlsi_mem_gen /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Parameters.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/utils/SRAMTemplate.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/PMA.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/L1plusCache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/L2Prefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/Prefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/StreamPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/csrc/common.cpp /XiangShan/src/test/csrc/compress.cpp /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala
2199a01c	25-Jan-2021	Allen <[email protected]>	Merge branch 'master' of github.com:RISCVERS/XiangShan into L1DCacheReTest /XiangShan/.github/workflows/emu.yml /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/block-inclusivecache-sifive /XiangShan/build.sc Makefile env.sh /XiangShan/scripts/utils/lock-emu.c /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/DataDontCareNode.scala /XiangShan/src/main/scala/utils/DataModuleTemplate.scala /XiangShan/src/main/scala/utils/ExcitingUtils.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/PriorityMuxGen.scala /XiangShan/src/main/scala/utils/SRAMTemplate.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/PMA.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FloatBlock.scala /XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/IndexMapping.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wb.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/AtomicsReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/DCache.scala /XiangShan/src/main/scala/xiangshan/cache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/InstrUncache.scala /XiangShan/src/main/scala/xiangshan/cache/L1plusCache.scala /XiangShan/src/main/scala/xiangshan/cache/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/Probe.scala /XiangShan/src/main/scala/xiangshan/cache/StoreReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/icacheMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/L1plusPrefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/L2Prefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/Prefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/StreamPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/NewLoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/sdcard.cpp /XiangShan/src/test/scala/cache/L1DTest/CoreAgent.scala /XiangShan/src/test/scala/cache/L1DTest/CoreTransatcion.scala /XiangShan/src/test/scala/cache/L1DTest/L1DTest.scala /XiangShan/src/test/scala/cache/L1plusCacheTest.scala /XiangShan/src/test/scala/cache/L2CacheNonInclusiveGetTest.scala /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/cache/TLCTest/TLCAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTest.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTransaction.scala /XiangShan/src/test/scala/cache/TLCTest/TLULAgent.scala /XiangShan/src/test/scala/cache/UnalignedGetTest.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/xiangshan/backend/issue/ReservationStationDataTest.scala /XiangShan/src/test/scala/xiangshan/memend/SbufferTest.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala /XiangShan/timingScripts
dfcfec89	22-Jan-2021	William Wang <[email protected]>	Merge remote-tracking branch 'origin/master' into opt-replay /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile Makefile /XiangShan/scripts/utils/lock-emu.c /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/utils/DataDontCareNode.scala /XiangShan/src/main/scala/utils/ExcitingUtils.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/SRAMWrapper.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FloatBlock.scala /XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wb.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/InstrUncache.scala /XiangShan/src/main/scala/xiangshan/cache/L1plusCache.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/icacheMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala
ec4b6291	22-Jan-2021	William Wang <[email protected]>	chore: add set debug envvar script /XiangShan/.github/workflows/emu.yml /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/berkeley-hardfloat /XiangShan/block-inclusivecache-sifive /XiangShan/build.sc env.sh /XiangShan/rocket-chip /XiangShan/scripts/autorun/README.md /XiangShan/scripts/autorun/common/__init__.py /XiangShan/scripts/autorun/common/local_config.py /XiangShan/scripts/autorun/common/simulator_task_goback.py /XiangShan/scripts/autorun/common/task_tree_go_back.py /XiangShan/scripts/autorun/config.py /XiangShan/scripts/autorun/run.py /XiangShan/scripts/coverage/coverage.py /XiangShan/scripts/coverage/statistics.py /XiangShan/scripts/utils/lock-emu.c /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Plic.scala /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Parameters.scala /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/DataModuleTemplate.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/PipelineConnect.scala /XiangShan/src/main/scala/utils/PriorityMuxGen.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/utils/SRAMWrapper.scala /XiangShan/src/main/scala/utils/TLDump.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/PMA.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FloatBlock.scala /XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Instructions.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/IndexMapping.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wb.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/L1plusCache.scala /XiangShan/src/main/scala/xiangshan/cache/atomics.scala /XiangShan/src/main/scala/xiangshan/cache/atomicsMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/icacheMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/L1plusPrefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/L2Prefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/Prefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/StreamPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/probe.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/storeMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/stu.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/cache/wbu.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/NewLoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/csrc/axi4.cpp /XiangShan/src/test/csrc/axi4.h /XiangShan/src/test/csrc/common.cpp /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/ram.h /XiangShan/src/test/csrc/sdcard.cpp /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/issue/ReservationStationDataTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala /XiangShan/src/test/scala/xiangshan/memend/SbufferTest.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala /XiangShan/src/test/vsrc/assert.v /XiangShan/timingScripts
367512b7	17-Jan-2021	jinyue110 <[email protected]>	Merge branch 'master' into icache-uncache /XiangShan/.github/workflows/emu.yml /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/berkeley-hardfloat /XiangShan/block-inclusivecache-sifive /XiangShan/build.sc cputest.sh /XiangShan/rocket-chip /XiangShan/scripts/autorun/README.md /XiangShan/scripts/autorun/common/__init__.py /XiangShan/scripts/autorun/common/local_config.py /XiangShan/scripts/autorun/common/simulator_task_goback.py /XiangShan/scripts/autorun/common/task_tree_go_back.py /XiangShan/scripts/autorun/config.py /XiangShan/scripts/autorun/run.py /XiangShan/scripts/coverage/coverage.py /XiangShan/scripts/coverage/statistics.py /XiangShan/scripts/utils/lock-emu.c /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Plic.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4SlaveModule.scala /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Parameters.scala /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/CircularQueuePtr.scala /XiangShan/src/main/scala/utils/DataModuleTemplate.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/ExtractVerilogModules.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/utils/PipelineConnect.scala /XiangShan/src/main/scala/utils/PriorityMuxGen.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/utils/SRAMWrapper.scala /XiangShan/src/main/scala/utils/TLDump.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FloatBlock.scala /XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Instructions.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/IndexMapping.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wb.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/L1plusCache.scala /XiangShan/src/main/scala/xiangshan/cache/atomics.scala /XiangShan/src/main/scala/xiangshan/cache/atomicsMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/icacheMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/icacheUncache.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/L1plusPrefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/L2Prefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/Prefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/StreamPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/probe.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/storeMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/stu.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/cache/wbu.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/NewLoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/csrc/axi4.cpp /XiangShan/src/test/csrc/axi4.h /XiangShan/src/test/csrc/common.cpp /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/compress.cpp /XiangShan/src/test/csrc/compress.h /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/ram.h /XiangShan/src/test/csrc/sdcard.cpp /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/csrc/snapshot.h /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/issue/ReservationStationDataTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala /XiangShan/src/test/scala/xiangshan/memend/SbufferTest.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala /XiangShan/src/test/vsrc/assert.v /XiangShan/timingScripts
b086c6da	13-Jan-2021	BigWhiteDog <[email protected]>	fix bug in core Agent /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/berkeley-hardfloat /XiangShan/block-inclusivecache-sifive Makefile /XiangShan/rocket-chip /XiangShan/scripts/autorun/README.md /XiangShan/scripts/autorun/common/__init__.py /XiangShan/scripts/autorun/common/local_config.py /XiangShan/scripts/autorun/common/simulator_task_goback.py /XiangShan/scripts/autorun/common/task_tree_go_back.py /XiangShan/scripts/autorun/config.py /XiangShan/scripts/autorun/run.py /XiangShan/scripts/utils/lock-emu.c /XiangShan/src/main/scala/device/AXI4Plic.scala /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Parameters.scala /XiangShan/src/main/scala/utils/DataModuleTemplate.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/PipelineConnect.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/utils/TLDump.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FloatBlock.scala /XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Instructions.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/IndexMapping.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSA.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/L1plusCache.scala /XiangShan/src/main/scala/xiangshan/cache/atomics.scala /XiangShan/src/main/scala/xiangshan/cache/atomicsMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/storeMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/stu.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/csrc/axi4.cpp /XiangShan/src/test/csrc/axi4.h /XiangShan/src/test/csrc/common.cpp /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/ram.h /XiangShan/src/test/scala/cache/L1DTest/CoreAgent.scala /XiangShan/src/test/scala/cache/L1DTest/CoreTransatcion.scala /XiangShan/src/test/scala/cache/L1DTest/L1DTest.scala /XiangShan/src/test/scala/cache/TLCTest/TLCAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTest.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTransaction.scala /XiangShan/src/test/scala/cache/TLCTest/TLSlaveMMIO.scala /XiangShan/src/test/scala/cache/TLCTest/TLULAgent.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala /XiangShan/src/test/vsrc/assert.v
d9469c00	23-Dec-2020	BigWhiteDog <[email protected]>	Merge branch 'master' into l2test /XiangShan/.github/workflows/emu.yml /XiangShan/.gitignore /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/block-inclusivecache-sifive /XiangShan/build.sc /XiangShan/chiseltest cputest.sh /XiangShan/rocket-chip /XiangShan/scripts/coverage/coverage.py /XiangShan/scripts/coverage/statistics.py /XiangShan/src/main/resources/vsrc/regfile_160x64_10w16r_sim.v /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4SlaveModule.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Parameters.scala /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/CircularQueuePtr.scala /XiangShan/src/main/scala/utils/ExtractVerilogModules.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/utils/PriorityMuxGen.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FloatBlock.scala /XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Instructions.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wb.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/F32toF64.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/F64toF32.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FCMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMV.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FloatToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFloat.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFloatSingleCycle.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/DivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/fma/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/L1plusCache.scala /XiangShan/src/main/scala/xiangshan/cache/atomicsMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/loadMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/storeMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/compress.cpp /XiangShan/src/test/csrc/compress.h /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/ram.h /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/csrc/snapshot.h /XiangShan/src/test/scala/cache/L2CacheNonInclusiveGetTest.scala /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/cache/TLCTest/BigIntUtil.scala /XiangShan/src/test/scala/cache/TLCTest/FixedBlockFuzzer.scala /XiangShan/src/test/scala/cache/TLCTest/TLCAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTest.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTransaction.scala /XiangShan/src/test/scala/cache/TLCTest/TLSlaveMMIO.scala /XiangShan/src/test/scala/cache/TLCTest/TLULAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLULMMIO.scala /XiangShan/src/test/scala/cache/UnalignedGetTest.scala /XiangShan/src/test/scala/device/AXI4BurstMaster.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/decode/DecodeUnitDiffTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala /XiangShan/src/test/vsrc/ram.v
49272fa4	22-Dec-2020	LinJiawei <[email protected]>	update cputest.sh /XiangShan/.github/workflows/emu.yml /XiangShan/.gitignore /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/block-inclusivecache-sifive /XiangShan/build.sc /XiangShan/chiseltest cputest.sh /XiangShan/rocket-chip /XiangShan/scripts/coverage/coverage.py /XiangShan/scripts/coverage/statistics.py /XiangShan/src/main/resources/vsrc/regfile_160x64_10w16r_sim.v /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/device/AXI4Keyboard.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4SlaveModule.scala /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/AXI4VGA.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Parameters.scala /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/CircularQueuePtr.scala /XiangShan/src/main/scala/utils/ExtractVerilogModules.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/utils/PriorityMuxGen.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FloatBlock.scala /XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Instructions.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wb.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/F32toF64.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/F64toF32.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FCMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMV.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FloatToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFloat.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFloatSingleCycle.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/DivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/fma/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/L1plusCache.scala /XiangShan/src/main/scala/xiangshan/cache/atomicsMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/loadMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/storeMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/compress.cpp /XiangShan/src/test/csrc/compress.h /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/ram.h /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/csrc/snapshot.h /XiangShan/src/test/scala/cache/L1plusCacheTest.scala /XiangShan/src/test/scala/cache/L2CacheNonInclusiveGetTest.scala /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/cache/UnalignedGetTest.scala /XiangShan/src/test/scala/device/AXI4BurstMaster.scala /XiangShan/src/test/scala/device/AXI4RamTest.scala /XiangShan/src/test/scala/device/AXI4TimerTest.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/decode/DecodeUnitDiffTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala /XiangShan/src/test/vsrc/ram.v
ab3aa7ee	09-Dec-2020	BigWhiteDog <[email protected]>	fix peek poke ordering /XiangShan/Makefile /XiangShan/block-inclusivecache-sifive Makefile /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/device/AXI4Keyboard.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4SlaveModule.scala /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/AXI4VGA.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/csrc/snapshot.h /XiangShan/src/test/scala/cache/L1plusCacheTest.scala /XiangShan/src/test/scala/cache/L2CacheNonInclusiveGetTest.scala /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/cache/TLCTest/TLCAgent.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTest.scala /XiangShan/src/test/scala/cache/TLCTest/TLCTransaction.scala /XiangShan/src/test/scala/cache/TLCTest/TLMasterMMIO.scala /XiangShan/src/test/scala/cache/TLCTest/TLSlaveMMIO.scala /XiangShan/src/test/scala/device/AXI4RamTest.scala /XiangShan/src/test/scala/device/AXI4TimerTest.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala
4b3d9f67	01-Dec-2020	jinyue110 <[email protected]>	add icache uncache support /XiangShan/.github/workflows/emu.yml /XiangShan/.gitignore /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/block-inclusivecache-sifive /XiangShan/build.sc /XiangShan/chiseltest Makefile /XiangShan/rocket-chip /XiangShan/src/main/resources/vsrc/regfile_160x64_10w16r_sim.v /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/device/AXI4Keyboard.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4SlaveModule.scala /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/AXI4VGA.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Parameters.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/FloatBlock.scala /XiangShan/src/main/scala/xiangshan/backend/IntegerBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wb.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/F32toF64.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/F64toF32.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FCMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMV.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FloatToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFloat.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFloatSingleCycle.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/DivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/fma/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/L1plusCache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/icacheUncache.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/test/csrc/common.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/ram.h /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/csrc/snapshot.h /XiangShan/src/test/scala/cache/L1plusCacheTest.scala /XiangShan/src/test/scala/cache/L2CacheNonInclusiveGetTest.scala /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/cache/UnalignedGetTest.scala /XiangShan/src/test/scala/device/AXI4BurstMaster.scala /XiangShan/src/test/scala/device/AXI4RamTest.scala /XiangShan/src/test/scala/device/AXI4TimerTest.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/vsrc/ram.v
6b98bdcb	18-Nov-2020	Lingrui98 <[email protected]>	SC: yet to debug sc_stat.sh /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
735e00f7	17-Nov-2020	Lingrui98 <[email protected]>	Merge remote-tracking branch 'origin/master' into tage-sc /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile cputest.sh /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/test/csrc/emu.cpp
3fce4f48	16-Nov-2020	Lingrui98 <[email protected]>	debug: add script to count sc performance /XiangShan/.github/workflows/emu.yml /XiangShan/.gitignore /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/api-config-chipsalliance /XiangShan/berkeley-hardfloat /XiangShan/block-inclusivecache-sifive /XiangShan/build.sc /XiangShan/chisel3 /XiangShan/chiseltest sc_stat.sh /XiangShan/firrtl /XiangShan/rocket-chip /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/F32toF64.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/F64toF32.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FCMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMV.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FloatToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFloat.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFloatSingleCycle.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/DivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/fma/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/icacheMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/cache/storeMissQueue.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/scala/cache/L1plusCacheTest.scala /XiangShan/src/test/scala/cache/L2CacheNonInclusiveGetTest.scala /XiangShan/src/test/scala/cache/L2CacheTest.scala /XiangShan/src/test/scala/device/AXI4RamTest.scala /XiangShan/src/test/scala/device/AXI4TimerTest.scala /XiangShan/src/test/scala/device/SimMMIOTest.scala /XiangShan/src/test/scala/device/TLTimerTest.scala /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/AluTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala /XiangShan/src/test/scala/xiangshan/frontend/PDtest.scala /XiangShan/src/test/scala/xiangshan/frontend/RASTest.scala /XiangShan/src/test/scala/xiangshan/frontend/uBTBTest.scala /XiangShan/src/test/scala/xiangshan/memend/SbufferTest.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala /XiangShan/treadle
10b9babd	11-Nov-2020	Lingrui98 <[email protected]>	merge serveral commits left in dev-frontend-loop /XiangShan/.github/workflows/emu.yml cputest.sh /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Fp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JumpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/F32toF64.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/F64toF32.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FCMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMV.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FloatToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFloat.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFloatSingleCycle.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/DivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/fma/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/icacheMissQueue.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/LoopPredictor.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala
a9ecfa67	08-Nov-2020	jinyue110 <[email protected]>	Merge branch 'master' into icache-l1plus fix conflicts in icache.scala and XSCore /XiangShan/.github/workflows/check-usage.sh /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile Makefile /XiangShan/dummy-riscv64-noop.txt /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/ParallelMux.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/utils/SRAMTemplate.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVC.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVD.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVF.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Int.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/DivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmacExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/FmiscExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/I2fExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/Classify.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/F32toF64.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/F64toF32.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FCMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMV.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FloatToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFloat.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFloatSingleCycle.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/README.md /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/RoundingUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/DivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/MantDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/OnTheFlyConv.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/divsqrt/SrtTable.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/fma/ArrayMultiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/fma/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/fma/LZA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/package.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/util/CarrySaveAdder.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/util/FPUDebug.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/util/ORTree.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/util/ShiftLeftJam.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/util/ShiftRightJam.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStationNew.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/atomics.scala /XiangShan/src/main/scala/xiangshan/cache/atomicsMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/ptw.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/separated/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/separated/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/separated/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/unified/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/scala/cache/CacheTest.scala /XiangShan/src/test/scala/cache/L1plusCacheTest.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/memend/SbufferTest.scala /XiangShan/src/test/scala/xiangshan/testutils/TestCaseGenerator.scala /XiangShan/src/test/vsrc/ram.v
043203e7	03-Nov-2020	jinyue110 <[email protected]>	icacheMissQueue: fix resp valid when needflush bug Makefile /XiangShan/src/main/scala/xiangshan/cache/icacheMissQueue.scala
b6f269e7	03-Nov-2020	jinyue110 <[email protected]>	icache: pipeline still going after branch flush still have bugs in cputests Makefile /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/icacheMissQueue.scala /XiangShan/src/test/csrc/emu.cpp
3136ee6a	02-Nov-2020	LinJiawei <[email protected]>	Merge 'master' into 'xs-fpu' /XiangShan/.github/workflows/emu.yml /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/block-inclusivecache-sifive /XiangShan/build.sc /XiangShan/chiseltest Makefile /XiangShan/rocket-chip /XiangShan/src/main/scala/utils/CircularQueuePtr.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/DivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/I2fExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/MulDivExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/package.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/probe.scala /XiangShan/src/main/scala/xiangshan/cache/wbu.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/separated/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/separated/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/separated/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/unified/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/NewSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xstransforms/PrintModuleName.scala /XiangShan/src/main/scala/xstransforms/ShowPrintTransform.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.cpp /XiangShan/src/test/csrc/sdcard.cpp /XiangShan/src/test/csrc/sdcard.h /XiangShan/src/test/csrc/uart.cpp /XiangShan/src/test/scala/cache/L2CacheTest.scala
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