| /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/ |
| H A D | PFEvent.scala | 17 val perfEvents: Seq[CSRModule[_]] = (0 until perfCntNum).map(num => constant
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| /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/ |
| H A D | MEFreeList.scala | 100 val perfEvents = Seq( constant
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| H A D | StdFreeList.scala | 116 val perfEvents = Seq( constant
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/ |
| H A D | Probe.scala | 227 val perfEvents = Seq( constant
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| H A D | WritebackQueue.scala | 404 val perfEvents = Seq( constant
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| /XiangShan/src/main/scala/xiangshan/mem/lsqueue/ |
| H A D | FreeList.scala | 135 val perfEvents: Seq[(String, UInt)] = Seq( constant
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| H A D | LoadQueueRAR.scala | 282 val perfEvents: Seq[(String, UInt)] = Seq( constant
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| H A D | LoadQueueRAW.scala | 372 val perfEvents: Seq[(String, UInt)] = Seq( constant
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| H A D | VirtualLoadQueue.scala | 288 val perfEvents: Seq[(String, UInt)] = Seq( constant
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| H A D | LoadQueueUncache.scala | 612 val perfEvents: Seq[(String, UInt)] = Seq( constant
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| H A D | LoadQueue.scala | 357 …val perfEvents = Seq(virtualLoadQueue, loadQueueRAR, loadQueueRAW, loadQueueReplay).flatMap(_.getP… constant
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| H A D | LSQWrapper.scala | 314 val perfEvents = Seq(loadQueue, storeQueue).flatMap(_.getPerfEvents) constant
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| /XiangShan/src/main/scala/xiangshan/ |
| H A D | XSCore.scala | 99 val perfEvents = Input(Vec(numPCntHc * coreParams.L2NBanks + 1, new PerfEvent)) constant
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| H A D | L2Top.scala | 217 val perfEvents = Output(Vec(numPCntHc * coreParams.L2NBanks + 1, new PerfEvent)) constant
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| /XiangShan/src/main/scala/xiangshan/backend/issue/ |
| H A D | Scheduler.scala | 369 val perfEvents = basePerfEvents constant
555 val perfEvents = basePerfEvents constant
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| /XiangShan/src/main/scala/xiangshan/backend/decode/ |
| H A D | DecodeStage.scala | 326 val perfEvents = Seq( constant
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| /XiangShan/src/main/scala/xiangshan/backend/rename/ |
| H A D | BusyTable.scala | 183 val perfEvents = Seq( constant
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| H A D | Rename.scala | 784 val perfEvents = renamePerf ++ intFlPerf ++ fpFlPerf ++ vecFlPerf ++ v0FlPerf ++ vlFlPerf constant
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| /XiangShan/src/main/scala/xiangshan/cache/mmu/ |
| H A D | L2TLB.scala | 782 val perfEvents = Seq(llptw, cache, ptw).flatMap(_.getPerfEvents) constant
967 val perfEvents = if (useSoftPTW) { constant
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| H A D | TLBStorage.scala | 260 val perfEvents = Seq( constant
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| /XiangShan/src/main/scala/xiangshan/frontend/ |
| H A D | IBuffer.scala | 490 val perfEvents = Seq( constant
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| H A D | BPU.scala | 209 val perfEvents: Seq[(String, UInt)] = Seq() constant
1215 val perfEvents = predictors.asInstanceOf[Composer].getPerfEvents constant
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| /XiangShan/src/main/scala/xiangshan/backend/datapath/ |
| H A D | DataPath.scala | 881 val perfEvents = Seq( constant
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| /XiangShan/src/main/scala/xiangshan/frontend/icache/ |
| H A D | ICache.scala | 754 val perfEvents: Seq[(String, Bool)] = Seq( constant
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/ |
| H A D | Uncache.scala | 603 val perfEvents = Seq( constant
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