| /XiangShan/src/main/scala/device/ |
| H A D | TLTimer.scala | 17 package device package
30 val device = new SimpleDevice("clint", Seq("XiangShan", "clint")) constant
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| H A D | AXI4Flash.scala | 17 package device package
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| H A D | AXI4UART.scala | 17 package device package
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| H A D | AXI4Keyboard.scala | 17 package device package
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| H A D | AXI4Timer.scala | 17 package device package
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| H A D | AXI4RAM.scala | 17 package device package
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| H A D | imsic_axi_top.scala | 17 package device package
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| H A D | AXI4SlaveModule.scala | 17 package device package
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| H A D | AXI4IntrGenerator.scala | 17 package device package
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| H A D | RocketDebugWrapper.scala | 18 package device package
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| H A D | AXI4DummySD.scala | 17 package device package
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| H A D | AXI4Plic.scala | 17 package device package
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| H A D | AXI4VGA.scala | 17 package device package
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| H A D | AXI4Memory.scala | 16 package device package
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| H A D | MemEncrypt.scala | 16 package device package
981 val device = new SimpleDevice("mem-encrypt-unit", Seq("iie,memencrypt0")) constant
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| H A D | MemEncryptUtil.scala | 16 package device package
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| /XiangShan/src/main/scala/device/TLPMA/ |
| H A D | TLPMA.scala | 1 package device package
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| /XiangShan/src/main/scala/xiangshan/ |
| H A D | XSDts.scala | 26 val device: SimpleDevice = new SimpleDevice("cpu", Seq("ICT,xiangshan", "riscv")) { constant
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| /XiangShan/src/main/scala/device/standalone/ |
| H A D | StandAloneDevice.scala | 211 val device: StandAloneDevice = module match { constant
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/ |
| H A D | CtrlUnit.scala | 65 val device: SimpleDevice = new SimpleDevice("L1DCacheCtrl", Seq("xiangshan,l1dcache_ctrl")) constant
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| /XiangShan/src/main/scala/xiangshan/frontend/icache/ |
| H A D | ICacheCtrlUnit.scala | 56 val device: SimpleDevice = new SimpleDevice("L1ICacheCtrl", Seq("xiangshan,l1icache_ctrl")) constant
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| /XiangShan/src/main/scala/system/ |
| H A D | SoC.scala | 279 val device = new MemoryDevice constant
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