| /XiangShan/src/main/scala/xiangshan/mem/lsqueue/ |
| H A D | LoadExceptionBuffer.scala | 50 val s1_valid = VecInit(io.req.map(x => x.valid)) constant
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| H A D | LoadQueueUncache.scala | 351 val s1_valid = VecInit(s1_sortedVec.map(_.valid)) constant
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| H A D | StoreMisalignBuffer.scala | 145 val s1_valid = VecInit(io.enq.map(x => x.req.valid)) constant
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| H A D | StoreQueue.scala | 92 val s1_valid = VecInit(io.storeAddrIn.map(x => constant
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| /XiangShan/src/main/scala/xiangshan/backend/rob/ |
| H A D | ExceptionGen.scala | 106 …val s1_valid = VecInit(s0_out_valid.zip(s0_out_bits).map{ case (v, b) => v && !(b.robIdx.needFlush… constant
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/storepipe/ |
| H A D | StorePipe.scala | 115 val s1_valid = RegNext(s0_fire) constant
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| /XiangShan/src/main/scala/xiangshan/mem/prefetch/ |
| H A D | L1StridePrefetcher.scala | 160 val s1_valid = GatedValidRegNext(s0_valid) constant
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| H A D | SMSPrefetcher.scala | 147 val s1_valid = Input(Bool()) constant
631 val s1_valid = Wire(Bool()) constant
950 val s1_valid = Wire(Bool()) constant
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| H A D | L1StreamPrefetcher.scala | 265 val s1_valid = GatedValidRegNext(s0_valid) constant
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| /XiangShan/src/main/scala/xiangshan/backend/datapath/ |
| H A D | DataPath.scala | 583 val s1_valid = s1_toExuValid(i)(j) constant
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| /XiangShan/src/main/scala/xiangshan/mem/pipeline/ |
| H A D | StoreUnit.scala | 279 val s1_valid = RegInit(false.B) constant
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| H A D | HybridUnit.scala | 541 val s1_valid = RegInit(false.B) constant
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| H A D | LoadUnit.scala | 901 val s1_valid = RegInit(false.B) constant
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| /XiangShan/src/main/scala/xiangshan/mem/vector/ |
| H A D | VSplit.scala | 182 val s1_valid = RegInit(false.B) constant
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/ |
| H A D | LoadPipe.scala | 175 val s1_valid = RegInit(false.B) constant
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| /XiangShan/src/main/scala/xiangshan/cache/mmu/ |
| H A D | TLB.scala | 424 val s1_valid = portTranslateEnable(idx) && !onlyS2 constant
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| /XiangShan/src/main/scala/xiangshan/frontend/ |
| H A D | ITTAGE.scala | 267 val s1_valid = RegNext(s0_valid) constant
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/ |
| H A D | MainPipe.scala | 297 val s1_valid = RegInit(false.B) constant
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