| /XiangShan/src/main/scala/xiangshan/mem/lsqueue/ |
| H A D | StoreQueueData.scala | 53 val data = Reg(Vec(numEntries, UInt(dataWidth.W))) constant
95 val data = UInt((XLEN/8).W) constant
107 val data = new Bundle() { constant
130 val data = Reg(Vec(numEntries, new SQData8Entry)) constant
274 val data = UInt(VLEN.W) constant
284 val data = new Bundle() { constant
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| /XiangShan/src/main/scala/xiangshan/backend/issue/ |
| H A D | DataArray.scala | 11 val data = Output(gen) constant
17 val data = Input(gen) constant
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| H A D | BypassNetwork.scala | 29 val data = UInt(dataBits.W) constant
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| /XiangShan/src/main/scala/xiangshan/backend/regcache/ |
| H A D | RegCacheDataModule.scala | 29 val data = Output(UInt(dataWidth.W)) constant
35 val data = Input(UInt(dataWidth.W)) constant
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| /XiangShan/src/main/scala/utils/ |
| H A D | AXI4Lite.scala | 33 val data = UInt(dataWidth.W) constant
38 val data = UInt(dataWidth.W) constant
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/ |
| H A D | WritebackQueue.scala | 49 val data = UInt((cfg.blockBytes * 8).W) constant
53 val data = UInt((cfg.blockBytes * 8).W) constant
99 val data = UInt((cfg.blockBytes * 8).W) constant
164 val data = Reg(UInt((cfg.blockBytes * 8).W)) constant
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| /XiangShan/src/main/scala/xiangshan/mem/mdp/ |
| H A D | WaitTable.scala | 45 val data = RegInit(VecInit(Seq.fill(WaitTableSize)(0.U(2.W)))) constant
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| /XiangShan/src/main/scala/xiangshan/backend/ |
| H A D | VecExcpDataMergeModule.scala | 618 val data = Vec(vlen / 8, UInt(8.W)) constant
624 val data = Vec(vlen / 16, UInt(16.W)) constant
630 val data = Vec(vlen / 32, UInt(32.W)) constant
636 val data = Vec(vlen / 64, UInt(64.W)) constant
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| /XiangShan/src/main/scala/xiangshan/mem/ |
| H A D | MaskedDataModule.scala | 50 val data = Reg(Vec(numEntries, gen)) constant
117 val data = Reg(Vec(numEntries, gen)) constant
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| /XiangShan/src/main/scala/xiangshan/backend/regfile/ |
| H A D | Regfile.scala | 29 val data = Output(UInt(dataWidth.W)) constant
35 val data = Input(UInt(dataWidth.W)) constant
51 val data = Input(UInt(rfWriteDataCfg.dataWidth.W)) constant
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| /XiangShan/tools/readmemh/ |
| H A D | groupby-4byte.c | 35 } data[4]; in main() local
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| /XiangShan/src/main/scala/xiangshan/mem/sbuffer/ |
| H A D | DatamoduleResultBuffer.scala | 50 val data = Reg(Vec(EnsbufferWidth, genType)) constant
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| /XiangShan/src/main/scala/xiangshan/backend/datapath/ |
| H A D | NewPipelineConnect.scala | 43 val data = RegEnable(left.bits, left.fire) constant
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| /XiangShan/src/main/scala/xiangshan/cache/mmu/ |
| H A D | BitmapCheck.scala | 56 val data = UInt(XLEN.W) constant
92 val data = UInt(XLEN.W) constant
342 val data = UInt(XLEN.W) constant
347 val data = UInt(XLEN.W) // store 64bits in one entry constant
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| /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/ |
| H A D | FPUSubModule.scala | 40 val data = UInt(64.W) constant
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| H A D | IntToFP.scala | 52 val data = UInt(XLEN.W) constant
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/data/ |
| H A D | AbstractDataArray.scala | 40 val data = Vec(blockRows, Bits(rowBits.W)) constant
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| H A D | BankedDataArray.scala | 73 val data = Vec(DCacheBanks, Bits(DCacheSRAMRowBits.W)) constant
95 val data = UInt(encDataBits.W) constant
104 val data = Input(UInt(encDataBits.W)) constant
110 val data = Output(UInt(encDataBits.W)) constant
171 val data = Output(Vec(DCacheWays, UInt(encDataBits.W))) constant
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| H A D | DuplicatedDataArray.scala | 160 val data = Cat(ecc_resp_chosen(k), data_resp_chosen(k)) constant
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| /XiangShan/src/main/scala/xiangshan/backend/fu/ |
| H A D | FunctionUnit.scala | 53 val data = UInt(len.W) constant
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| /XiangShan/src/main/scala/xiangshan/frontend/icache/ |
| H A D | InstrUncache.scala | 41 val data: UInt = UInt(maxInstrLen.W) constant
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| H A D | ICacheBundle.scala | 54 val data: UInt = UInt(blockBits.W) constant
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| /XiangShan/src/main/scala/xiangshan/cache/dcache/ |
| H A D | DCacheWrapper.scala | 373 val data = UInt(VLEN.W) constant
394 val data = UInt((cfg.blockBytes * 8).W) constant
435 val data = UInt(VLEN.W) constant
481 val data = UInt((cfg.blockBytes * 8).W) constant
496 val data = UInt(l1BusDataWidth.W) constant
528 val data = UInt(XLEN.W) constant
553 val data = UInt(XLEN.W) constant
583 val data = UInt(QuadWordBits.W) constant
672 val data = UInt(l1BusDataWidth.W) constant
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| /XiangShan/src/main/scala/xiangshan/frontend/ |
| H A D | PreDecode.scala | 101 val data = io.in.bits.data constant
456 val data = if (HasCExtension) Input(Vec(PredictWidth + 1, UInt(16.W))) constant
460 val data = io.data constant
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| /XiangShan/src/main/scala/xiangshan/backend/rename/ |
| H A D | RenameTable.scala | 38 val data = Output(UInt(PhyRegIdxWidth.W)) constant
44 val data = UInt(PhyRegIdxWidth.W) constant
|