ctrlblock - OpenGrok history log for /XiangShan/src/main/scala/xiangshan/backend/ctrlblock

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
51aa1b60	02-Jan-2025	xiaofeibao-xjtu <[email protected]>	fix(redirectGen): fix bug of csr's cfiUpdate (#4118) /XiangShan/.github/CODEOWNERS /XiangShan/.github/workflows/perf.yml /XiangShan/Makefile /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/openLLC /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/device/AXI4SlaveModule.scala /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/TLDump.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/L2Top.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala RedirectGenerator.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRCustom.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PMPEntryModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FpPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Snapshot.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala /XiangShan/src/main/scala/xiangshan/backend/rob/RobDeqPtrWrapper.scala /XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/trace/Interface.scala /XiangShan/src/main/scala/xiangshan/backend/trace/Trace.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheCtrlUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala /XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/WaitTable.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala /XiangShan/src/main/scala/xiangshan/transforms/PrintModuleName.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/utility
7da4513b	05-Dec-2024	xiaofeibao <[email protected]>	timing(redirectGen): fix timing of addr trans type exception /XiangShan/.github/filters.yaml /XiangShan/.github/workflows/emu.yml /XiangShan/.github/workflows/format.yml /XiangShan/.github/workflows/perf.yml /XiangShan/.gitignore /XiangShan/.mill-version /XiangShan/.scalafmt.conf /XiangShan/Makefile /XiangShan/README.md /XiangShan/build.sc /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/huancun /XiangShan/images/xs-arch-kunminghu.svg /XiangShan/openLLC /XiangShan/readme.zh-cn.md /XiangShan/ready-to-run /XiangShan/rocket-chip /XiangShan/scripts/generate_all.sh /XiangShan/scripts/parser.py /XiangShan/scripts/xiangshan.py /XiangShan/src/main/resources/aia /XiangShan/src/main/scala/device/AXI4IntrGenerator.scala /XiangShan/src/main/scala/device/IMSIC.scala /XiangShan/src/main/scala/device/IMSICAsync.scala /XiangShan/src/main/scala/device/RocketDebugWrapper.scala /XiangShan/src/main/scala/device/imsic_axi_top.scala /XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala /XiangShan/src/main/scala/device/standalone/StandAloneDevice.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/top/XSNoCTop.scala /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/AXI4Lite.scala /XiangShan/src/main/scala/utils/SeqUtils.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/DbEntry.scala /XiangShan/src/main/scala/xiangshan/L2Top.scala /XiangShan/src/main/scala/xiangshan/PMParameters.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSDts.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/XSTileWrap.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/README.md /XiangShan/src/main/scala/xiangshan/backend/VecExcpDataMergeModule.scala RedirectGenerator.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/Og2ForVector.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Instructions.scala /XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2IqFpImp.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/DretEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MNretEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MretEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/SretEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryDEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMNEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRFields.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CommitIDModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/ExceptionBundle.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptBundle.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PMPEntryModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapInstMod.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapTvalMod.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FliTable.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntFPToVec.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/BranchUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FCVT.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheTagModule.scala /XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheTagTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/CompressUnit.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/ExceptionGen.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala /XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/trace/Interface.scala /XiangShan/src/main/scala/xiangshan/backend/trace/Trace.scala /XiangShan/src/main/scala/xiangshan/backend/trace/TraceBuffer.scala /XiangShan/src/main/scala/xiangshan/cache/CacheConstants.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/CtrlUnit.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AMOALU.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/AsynchronousMetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/storepipe/StorePipe.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Composer.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/README.md /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/FIFO.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala /XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/WaitTable.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/FDP.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchInterface.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StreamPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/PrefetcherMonitor.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VfofBuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/utility /XiangShan/yunsuan
a9627d0e	01-Sep-2024	xiaofeibao <[email protected]>	perf(ssit): allocate upon the first violation Co-authored-by: weidingliu /XiangShan/.github/workflows/check_verilog.py /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile /XiangShan/README.md /XiangShan/build.sc /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/openLLC /XiangShan/ready-to-run /XiangShan/scripts/xiangshan.py /XiangShan/src/main/resources/aia /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/device/IMSIC.scala /XiangShan/src/main/scala/device/IMSICAsync.scala /XiangShan/src/main/scala/device/standalone/StandAloneCLINT.scala /XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala /XiangShan/src/main/scala/device/standalone/StandAlonePLIC.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/top/XSNoCTop.scala /XiangShan/src/main/scala/utils/NamedUInt.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/L2Top.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/XSTileWrap.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/PipeGroupConnect.scala RedirectGenerator.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataConfig.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataSource.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRCustom.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryDEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptBundle.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapInstMod.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FCVT.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/regcache/AgeDetector.scala /XiangShan/src/main/scala/xiangshan/backend/regcache/RegCache.scala /XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheAgeTimer.scala /XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheDataModule.scala /XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheTagModule.scala /XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheTagTable.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/CompressUnit.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/ExceptionGen.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala /XiangShan/src/main/scala/xiangshan/backend/trace/Interface.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala /XiangShan/src/main/scala/xiangshan/cache/wpu/VictimList.scala /XiangShan/src/main/scala/xiangshan/cache/wpu/WPUWrapper.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala /XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/utility /XiangShan/yunsuan
62ff531e	24-Jul-2024	xiaofeibao <[email protected]>	MemCtrl: disble mdp for better performance /XiangShan/.github/workflows/emu.yml /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala RedirectGenerator.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryDEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala /XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala /XiangShan/src/main/scala/xiangshan/backend/rob/ExceptionGen.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala /XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/yunsuan
54c6d89d	24-Jul-2024	xiaofeibao-xjtu <[email protected]>	Redirect fix timing (#3209) /XiangShan/.github/CODEOWNERS /XiangShan/.github/ISSUE_TEMPLATE/1-bug_report.yml /XiangShan/.github/ISSUE_TEMPLATE/2-feature_request.yaml /XiangShan/.github/ISSUE_TEMPLATE/3-problem.yaml /XiangShan/.github/ISSUE_TEMPLATE/4-other_question.yml /XiangShan/.github/filters.yaml /XiangShan/.github/workflows/check_verilog.py /XiangShan/.github/workflows/emu.yml /XiangShan/.github/workflows/nightly.yml /XiangShan/.gitignore /XiangShan/.gitmodules /XiangShan/.mill-version /XiangShan/Makefile /XiangShan/build.sc /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/huancun /XiangShan/macros/src/main/scala/CSRMacros.scala /XiangShan/openLLC /XiangShan/ready-to-run /XiangShan/rocket-chip /XiangShan/scripts/xiangshan.py /XiangShan/src/main/resources/aia /XiangShan/src/main/scala/device/AXI4Memory.scala /XiangShan/src/main/scala/device/AXI4Plic.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/IMSIC.scala /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/device/imsic_axi_top.scala /XiangShan/src/main/scala/device/standalone/StandAloneCLINT.scala /XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala /XiangShan/src/main/scala/device/standalone/StandAloneDevice.scala /XiangShan/src/main/scala/device/standalone/StandAlonePLIC.scala /XiangShan/src/main/scala/device/standalone/standalone_device.mk /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/BusPerfMonitor.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Generator.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/top/XSNoCTop.scala /XiangShan/src/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/utils/AXI4Lite.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/DebugMem.scala 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/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/FDP.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StreamPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/PrefetcherMonitor.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xiangshan/transforms/Helpers.scala /XiangShan/src/main/scala/xiangshan/transforms/NestedPrefixModulesAnnotation.scala /XiangShan/src/main/scala/xiangshan/transforms/PrintControl.scala /XiangShan/src/main/scala/xiangshan/transforms/PrintModuleName.scala /XiangShan/src/test/scala/fu/IntDiv.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/src/test/scala/xiangshan/DecodeTest.scala /XiangShan/src/test/scala/xiangshan/XSTester.scala /XiangShan/src/test/scala/xiangshan/backend/BackendMain.scala /XiangShan/src/test/scala/xiangshan/backend/fu/vector/ByteMaskTailGenTest.scala /XiangShan/utility /XiangShan/yunsuan
ac4d321d	14-Apr-2024	Xuan Hu <[email protected]>	Merge remote-tracking branch 'ssh_upstream/master' into tmp-master /XiangShan/.github/ISSUE_TEMPLATE/1-bug_report.md /XiangShan/.github/ISSUE_TEMPLATE/2-feature_request.md /XiangShan/.github/ISSUE_TEMPLATE/3-problem.md /XiangShan/.github/ISSUE_TEMPLATE/4-other_question.md /XiangShan/.github/ISSUE_TEMPLATE/config.yml /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile /XiangShan/build.sc /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/fudian /XiangShan/huancun /XiangShan/ready-to-run /XiangShan/rocket-chip /XiangShan/scripts/vlsi_mem_gen /XiangShan/scripts/xiangshan.py /XiangShan/src/chisel/main/scala/top/XiangShanStage.scala /XiangShan/src/main/scala/device/AXI4Memory.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/Trigger.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/L2Top.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSDts.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala LsInfo.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RFWBConflictChecker.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/Trigger.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/issue/AgeDetector.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/NewAgeDetector.scala /XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/FakeDCache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLBMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TlbPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StreamPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/DatamoduleResultBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/StorePrefetchBursts.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSFlowQueue.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xiangshan/transforms/NestedPrefixModulesAnnotation.scala /XiangShan/utility /XiangShan/yunsuan
5f8b6c9e	07-Mar-2024	sinceforYy <[email protected]>	Backend: add clock gating to valid singal /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala RedirectGenerator.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
9477429f	07-Mar-2024	sinceforYy <[email protected]>	Backend: add ren signal to SyncDataModuleTemplate /XiangShan/Makefile /XiangShan/huancun /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/utils/ClockGate.scala /XiangShan/src/main/scala/utils/PipeWithFlush.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala MemCtrl.scala RedirectGenerator.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataConfig.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataSource.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RFReadArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RFWBConflictChecker.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WakeUpConfig.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbConfig.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Instructions.scala /XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntFPToVec.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecNonPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/BranchUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIDiv.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala /XiangShan/src/main/scala/xiangshan/backend/issue/AgeDetector.scala /XiangShan/src/main/scala/xiangshan/backend/issue/CancelNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EnqPolicy.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala /XiangShan/src/main/scala/xiangshan/backend/issue/FuBusyTableRead.scala /XiangShan/src/main/scala/xiangshan/backend/issue/FuBusyTableWrite.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ImmExtractor.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/MultiWakeupQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/NewAgeDetector.scala /XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/PregParams.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBankedArray.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/FreeList.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/StorePrefetchBursts.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VLFlowQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VLUopQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSFlowQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSUopQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/xiangshan/backend/issue/MultiWakeupQueueMain.scala /XiangShan/src/test/scala/xiangshan/utils/GenPipeWithFlush.scala /XiangShan/utility /XiangShan/yunsuan
272ec6b1	14-Dec-2023	Haojin Tang <[email protected]>	stIn: connect missing wire /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala MemCtrl.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgtu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VLFlowQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VLUopQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSFlowQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala /XiangShan/yunsuan
643734bb	03-Jan-2024	Xuan Hu <[email protected]>	Backend: fix load replay next inst * fix the situation that load violation not flush itself /XiangShan/Makefile /XiangShan/build.sc /XiangShan/difftest /XiangShan/scripts/top-down/.gitignore /XiangShan/scripts/top-down/README.md /XiangShan/scripts/top-down/configs.py /XiangShan/scripts/top-down/draw.py /XiangShan/scripts/top-down/resources/spec06_rv64gcb_o2_20m.json /XiangShan/scripts/top-down/top_down.py /XiangShan/scripts/top-down/utils.py /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala RedirectGenerator.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecNonPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VLFlowQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VLUopQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VLWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSFlowQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSUopQueue.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/utility /XiangShan/yunsuan
e4d4d305	24-Dec-2023	Xuan Hu <[email protected]>	MemBlock: fix the order of tlb ports of mem exus * The mem exu ord should as follows, * load * hybrid load part(if exists) * store addr * store data * hybrid store part * TODO: refactor th MemBlock: fix the order of tlb ports of mem exus * The mem exu ord should as follows, * load * hybrid load part(if exists) * store addr * store data * hybrid store part * TODO: refactor the fxxking port connections using indexes-independent method show more ... /XiangShan/.github/CODEOWNERS /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile /XiangShan/README.md /XiangShan/build.sc /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/huancun /XiangShan/readme.zh-cn.md /XiangShan/scripts/sram_size_collect.py /XiangShan/scripts/xiangshan.py /XiangShan/src/chisel/main/scala/top/XiangShanStage.scala /XiangShan/src/chisel/main/scala/xiangshan/transforms/Helpers.scala /XiangShan/src/chisel/main/scala/xiangshan/transforms/PrintControl.scala /XiangShan/src/chisel/main/scala/xiangshan/transforms/PrintModuleName.scala /XiangShan/src/chisel/main/scala/xiangshan/types.scala /XiangShan/src/chisel/test/scala/xiangshan/types.scala /XiangShan/src/chisel3/main/scala/top/XiangShanStage.scala /XiangShan/src/chisel3/main/scala/xiangshan/transforms/PrintControl.scala /XiangShan/src/chisel3/main/scala/xiangshan/transforms/PrintModuleName.scala /XiangShan/src/chisel3/main/scala/xiangshan/types.scala /XiangShan/src/chisel3/test/scala/xiangshan/types.scala /XiangShan/src/main/scala/device/AXI4Memory.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Generator.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/ClockGate.scala /XiangShan/src/main/scala/utils/PerfCounterUtils.scala /XiangShan/src/main/scala/utils/Trigger.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/L2Top.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSDts.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala LsInfo.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Vsetu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToVec.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/FakeDCache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Composer.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBankedArray.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VLFlowQueue.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/main/scala/xiangshan/transforms/PrintControl.scala /XiangShan/src/test/scala/fu/IntDiv.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/src/test/scala/xiangshan/DecodeTest.scala /XiangShan/utility
3827c997	01-Nov-2023	sinceforYy <[email protected]>	Backend: add en to RegNext /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala RedirectGenerator.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
b1e92023	26-Oct-2023	sinceforYy <[email protected]>	CtrlBlock: add en to RegNext /XiangShan/src/main/scala/device/RocketDebugWrapper.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/BitsUtils.scala /XiangShan/src/main/scala/utils/Trigger.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala RedirectGenerator.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/OldestFirstArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/DebugCSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/Trigger.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/ByteMaskTailGen.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/FDP.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VLFlowQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VLUopQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VLWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSFlowQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VSUopQueue.scala /XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/utility
8f1fa9b1	23-Oct-2023	sfencevma <[email protected]>	add hybrid unit /XiangShan/build.sc /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/top/BusPerfMonitor.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/utils/MathUtils.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala LsInfo.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RFReadArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbFuBusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToVec.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CSR/CSRNamedConstant.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala /XiangShan/src/main/scala/xiangshan/backend/issue/CancelNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Snapshot.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/FDP.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
6ce10964	12-Oct-2023	Xuan Hu <[email protected]>	fix merge errors /XiangShan/Makefile /XiangShan/build.sc /XiangShan/coupledL2 /XiangShan/fudian /XiangShan/huancun /XiangShan/scripts/split_verilog.sh /XiangShan/scripts/vlsi_mem_gen /XiangShan/src-chisel/main/scala/xiangshan/types.scala /XiangShan/src-chisel/test/scala/xiangshan/types.scala /XiangShan/src-chisel3/main/scala/top/XiangShanStage.scala /XiangShan/src-chisel3/main/scala/xiangshan/types.scala /XiangShan/src-chisel3/main/scala/xstransforms/PrintControl.scala /XiangShan/src-chisel3/main/scala/xstransforms/PrintModuleName.scala /XiangShan/src-chisel3/test/scala/xiangshan/types.scala /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Generator.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/DebugMem.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala RedirectGenerator.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/utils/UIntToCont0s.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/utils/UIntToCont1s.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/test/scala/fu/IntDiv.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/src/test/scala/xiangshan/DecodeTest.scala /XiangShan/src/test/scala/xiangshan/XSTester.scala /XiangShan/src/test/scala/xiangshan/backend/BackendMain.scala /XiangShan/src/test/scala/xiangshan/backend/DataPathMain.scala /XiangShan/src/test/scala/xiangshan/backend/SchedulerMain.scala /XiangShan/src/test/scala/xiangshan/backend/dispatch/Dispatch2IqMain.scala /XiangShan/src/test/scala/xiangshan/backend/issue/DataArrayMain.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueMain.scala /XiangShan/src/test/scala/xiangshan/backend/issue/MultiWakeupQueueMain.scala /XiangShan/src/test/scala/xiangshan/utils/GenPipeWithFlush.scala
83ba63b3	11-Oct-2023	Xuan Hu <[email protected]>	fix merge error /XiangShan/.github/workflows/check_verilog.py /XiangShan/Makefile /XiangShan/build.sc /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/fudian /XiangShan/huancun /XiangShan/ready-to-run /XiangShan/rocket-chip /XiangShan/scripts/cache/convert_dir.sh /XiangShan/scripts/cache/convert_mp.sh /XiangShan/scripts/cache/convert_tllog.sh /XiangShan/scripts/cache/l2DB_helper.py /XiangShan/scripts/cache/parseAddr.py /XiangShan/scripts/rolling/rolling.py /XiangShan/scripts/rolling/rollingplot.py /XiangShan/scripts/xiangshan.py /XiangShan/src/main/scala/device/AXI4DummySD.scala /XiangShan/src/main/scala/device/AXI4Flash.scala /XiangShan/src/main/scala/device/AXI4IntrGenerator.scala /XiangShan/src/main/scala/device/AXI4Keyboard.scala /XiangShan/src/main/scala/device/AXI4Memory.scala /XiangShan/src/main/scala/device/AXI4Plic.scala /XiangShan/src/main/scala/device/AXI4RAM.scala /XiangShan/src/main/scala/device/AXI4SlaveModule.scala /XiangShan/src/main/scala/device/AXI4Timer.scala /XiangShan/src/main/scala/device/AXI4UART.scala /XiangShan/src/main/scala/device/AXI4VGA.scala /XiangShan/src/main/scala/device/RocketDebugWrapper.scala /XiangShan/src/main/scala/device/TLPMA/TLPMA.scala /XiangShan/src/main/scala/device/TLTimer.scala /XiangShan/src/main/scala/gpu/GPU.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/BusPerfMonitor.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Generator.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/ArbiterHelper.scala /XiangShan/src/main/scala/utils/DataDontCareNode.scala /XiangShan/src/main/scala/utils/DebugIdentityNode.scala /XiangShan/src/main/scala/utils/EnumUtils.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/PerfCounterUtils.scala /XiangShan/src/main/scala/utils/PipeWithFlush.scala /XiangShan/src/main/scala/utils/TLDump.scala /XiangShan/src/main/scala/utils/Trigger.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/DbEntry.scala /XiangShan/src/main/scala/xiangshan/PMParameters.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSDts.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala LsInfo.scala MemCtrl.scala RedirectGenerator.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/NewPipelineConnect.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RFReadArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RFWBConflictChecker.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WakeUpConfig.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiterParams.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbFuBusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/IndexMapping.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Bku.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Branch.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/InputBuffer.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Radix2Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Vsetu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/util/CryptoUtils.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/ByteMaskTailGen.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgtu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VFPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIMacU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VPerm.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecNonPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/BranchUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/DivUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/MulUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala /XiangShan/src/main/scala/xiangshan/backend/implicitCast.scala /XiangShan/src/main/scala/xiangshan/backend/issue/AgeDetector.scala /XiangShan/src/main/scala/xiangshan/backend/issue/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/issue/CancelNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/DeqPolicy.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EnqPolicy.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala /XiangShan/src/main/scala/xiangshan/backend/issue/FuBusyTableRead.scala /XiangShan/src/main/scala/xiangshan/backend/issue/FuBusyTableWrite.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ImmExtractor.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/MultiWakeupQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/NewAgeDetector.scala /XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/issue/WakeupQueue.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/CompressUnit.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Snapshot.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/RefCounter.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/CacheInstruction.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/FakeDCache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/RefillPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/AsynchronousMetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/storepipe/StorePipe.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLBMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TlbPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/BestOffsetPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/Prefetcher.scala /XiangShan/src/main/scala/xiangshan/cache/prefetch/StreamPrefetch.scala /XiangShan/src/main/scala/xiangshan/cache/wpu/VictimList.scala /XiangShan/src/main/scala/xiangshan/cache/wpu/WPU.scala /XiangShan/src/main/scala/xiangshan/cache/wpu/WPUWrapper.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Composer.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBankedArray.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala /XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/MemTrace.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/FreeList.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/WaitTable.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/FDP.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchInterface.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StreamPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/PrefetcherMonitor.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/DatamoduleResultBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/StorePrefetchBursts.scala /XiangShan/src/main/scala/xiangshan/mem/vector/DummyVLSQ.scala /XiangShan/src/main/scala/xiangshan/mem/vector/MemVectorInterface.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/src/test/scala/xiangshan/DecodeTest.scala /XiangShan/src/test/scala/xiangshan/XSTester.scala /XiangShan/src/test/scala/xiangshan/backend/BackendMain.scala /XiangShan/src/test/scala/xiangshan/backend/DataPathMain.scala /XiangShan/src/test/scala/xiangshan/backend/SchedulerMain.scala /XiangShan/src/test/scala/xiangshan/backend/dispatch/Dispatch2IqMain.scala /XiangShan/src/test/scala/xiangshan/backend/fu/VsetTop.scala /XiangShan/src/test/scala/xiangshan/backend/issue/DataArrayMain.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueMain.scala /XiangShan/src/test/scala/xiangshan/backend/issue/MultiWakeupQueueMain.scala /XiangShan/src/test/scala/xiangshan/utils/GenPipeWithFlush.scala /XiangShan/utility /XiangShan/yunsuan
870f462d	11-Aug-2023	Xuan Hu <[email protected]>	fix errors in merge master into new-backend /XiangShan/.mill-version /XiangShan/Makefile /XiangShan/build.sc /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/huancun /XiangShan/rocket-chip /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/BusPerfMonitor.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/PerfCounterUtils.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/DbEntry.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala LsInfo.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/predecode/predecode.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Snapshot.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/RefillPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/wpu/VictimList.scala /XiangShan/src/main/scala/xiangshan/cache/wpu/WPU.scala /XiangShan/src/main/scala/xiangshan/cache/wpu/WPUWrapper.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/FTB.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/SC.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/FreeList.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/cache/WpuTest.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/utility
24519898	06-Aug-2023	Xuan Hu <[email protected]>	backend: refactor * Prepare for merge master /XiangShan/Makefile /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/utils/BundleUtils.scala /XiangShan/src/main/scala/utils/MapUtils.scala /XiangShan/src/main/scala/utils/MathUtils.scala /XiangShan/src/main/scala/utils/OptionWrapper.scala /XiangShan/src/main/scala/utils/PipeWithFlush.scala /XiangShan/src/main/scala/utils/SeqUtils.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/DbEntry.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala LsInfo.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataConfig.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataSource.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RFReadArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RFWBConflictChecker.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RdConfig.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WakeUpConfig.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiterParams.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbConfig.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbFuBusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecNonPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala /XiangShan/src/main/scala/xiangshan/backend/issue/CancelNetwork.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/FuBusyTableRead.scala /XiangShan/src/main/scala/xiangshan/backend/issue/FuBusyTableWrite.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/MultiWakeupQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/PregParams.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/xiangshan/DecodeTest.scala /XiangShan/src/test/scala/xiangshan/XSTester.scala /XiangShan/src/test/scala/xiangshan/backend/BackendMain.scala /XiangShan/src/test/scala/xiangshan/backend/issue/MultiWakeupQueueMain.scala /XiangShan/src/test/scala/xiangshan/utils/GenPipeWithFlush.scala /XiangShan/yunsuan
92b88f30	11-Jun-2023	fdy <[email protected]>	CtrlBlock: fix a bug of walkVType /XiangShan/.gitmodules /XiangShan/Makefile /XiangShan/build.sc /XiangShan/coupledL2 /XiangShan/difftest /XiangShan/huancun /XiangShan/rocket-chip /XiangShan/scripts/xiangshan.py /XiangShan/src/main/resources/espresso /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/NamedUInt.scala /XiangShan/src/main/scala/utils/OptionWrapper.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/NewPipelineConnect.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RdConfig.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiterParams.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbConfig.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Bku.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/ByteMaskTailGen.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Utils.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VFPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIMacU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VPerm.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecSrcTypeModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/utils/MaskExtrator.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/utils/ScalaDupToVector.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/utils/UIntToCont0s.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/utils/UIntToCont1s.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/utils/VecDataSplitModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/BranchUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/DivUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/MulUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ImmExtractor.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/WakeupQueue.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBankedArray.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/FreeList.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/src/test/scala/xiangshan/backend/fu/VsetTop.scala /XiangShan/src/test/scala/xiangshan/backend/fu/vector/ByteMaskTailGenTest.scala /XiangShan/utility /XiangShan/yunsuan
a8db15d8	10-May-2023	fdy <[email protected]>	backend: refactor vset and add rab support /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Vsetu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/RefCounter.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/xiangshan/backend/fu/VsetModuleMain.scala /XiangShan/src/test/scala/xiangshan/backend/fu/VsetRef.scala /XiangShan/src/test/scala/xiangshan/backend/fu/VsetTop.scala
b52d4755	26-Apr-2023	Xuan Hu <[email protected]>	isa-riscv,vector: add bundles and convert function * Add class VType, VConfig * Add object VSew, VLmul /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala
d91483a6	28-Apr-2023	fdy <[email protected]>	add vset support Co-authored-by: zhanglyGit <[email protected]> Co-authored-by: Xuan Hu <[email protected]> /XiangShan/difftest /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Bku.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Vsetu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/MulUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ImmExtractor.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala /XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/yunsuan
8a00ff56	21-Apr-2023	Xuan Hu <[email protected]>	backend: fix merge master error /XiangShan/Makefile /XiangShan/Makefile.test /XiangShan/build.sc /XiangShan/debug/local_ci.py /XiangShan/difftest /XiangShan/scripts/constantHelper.py /XiangShan/scripts/gen_sep_mem.sh /XiangShan/scripts/top-down/README.md /XiangShan/scripts/top-down/top-down.sh /XiangShan/scripts/top-down/top_down.py /XiangShan/scripts/utils/convert.sh /XiangShan/src/main/scala/top/ArgParser.scala /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/top/Generator.scala /XiangShan/src/main/scala/top/Top.scala /XiangShan/src/main/scala/utils/ArbiterHelper.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/OverrideableQueue.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/DbEntry.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/XSTile.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala /XiangShan/src/main/scala/xiangshan/backend/Scheduler.scala CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/cache/CacheInstruction.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/RefillPipe.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/AsynchronousMetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala /XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala /XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala /XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/MemTrace.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchInterface.scala /XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/fu/IntDiv.scala /XiangShan/src/test/scala/top/SimTop.scala /XiangShan/src/test/scala/xiangshan/DecodeTest.scala /XiangShan/src/test/scala/xiangshan/XSTester.scala /XiangShan/src/test/scala/xiangshan/backend/BackendMain.scala /XiangShan/src/test/scala/xiangshan/backend/DataPathMain.scala /XiangShan/src/test/scala/xiangshan/backend/SchedulerMain.scala /XiangShan/src/test/scala/xiangshan/backend/dispatch/Dispatch2IqMain.scala /XiangShan/src/test/scala/xiangshan/backend/issue/DataArrayMain.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueMain.scala /XiangShan/src/test/scala/xiangshan/backend/issue/StatusArrayMain.scala /XiangShan/utility
730cfbc0	16-Apr-2023	Xuan Hu <[email protected]>	backend: merge v2backend into backend /XiangShan/src/main/scala/top/Configs.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala CtrlBlock.scala MemCtrl.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataConfig.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/RdConfig.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiterParams.scala /XiangShan/src/main/scala/xiangshan/backend/datapath/WbConfig.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala /XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Bku.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FDivSqrt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FMA.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPToInt.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPUSubModule.scala /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala /XiangShan/src/main/scala/xiangshan/backend/fu/vector/VIPU.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/BranchUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/DivUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/MulUnit.scala /XiangShan/src/main/scala/xiangshan/backend/issue/AgeDetector.scala /XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala /XiangShan/src/main/scala/xiangshan/backend/issue/DeqPolicy.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/backend/issue/EnqPolicy.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ImmExtractor.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala /XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala /XiangShan/src/main/scala/xiangshan/backend/issue/StatusArray.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/PregParams.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/mem/vector/MemVectorInterface.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/xiangshan/backend/BackendMain.scala /XiangShan/src/test/scala/xiangshan/backend/DataPathMain.scala /XiangShan/src/test/scala/xiangshan/backend/SchedulerMain.scala /XiangShan/src/test/scala/xiangshan/backend/dispatch/Dispatch2IqMain.scala /XiangShan/src/test/scala/xiangshan/backend/issue/DataArrayMain.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueMain.scala /XiangShan/src/test/scala/xiangshan/backend/issue/StatusArrayMain.scala
141a6449	27-Mar-2023	Xuan Hu <[email protected]>	backend: add load inst support /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/Parameters.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala /XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala MemCtrl.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Branch.scala /XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala /XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala /XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala /XiangShan/src/main/scala/xiangshan/v2backend/Backend.scala /XiangShan/src/main/scala/xiangshan/v2backend/BackendParams.scala /XiangShan/src/main/scala/xiangshan/v2backend/Bundles.scala /XiangShan/src/main/scala/xiangshan/v2backend/DataPath.scala /XiangShan/src/main/scala/xiangshan/v2backend/ExuBlock.scala /XiangShan/src/main/scala/xiangshan/v2backend/Scheduler.scala /XiangShan/src/main/scala/xiangshan/v2backend/dispatch/Dispatch2Iq.scala /XiangShan/src/main/scala/xiangshan/v2backend/exu/ExeUnit.scala /XiangShan/src/main/scala/xiangshan/v2backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/v2backend/issue/StatusArray.scala /XiangShan/src/main/scala/xiangshan/v2backend/package.scala
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