/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/ |
H A D | LegacyMetaArray.scala | 63 val error = Output(ValidIO(new L1CacheErrorInfo)) constant 92 cacheParams.tagCode.decode(d).error && RegNext(io.read.bits.way_en(w)) 94 io.error.bits.report_to_beu := RegNext(io.read.fire) && Cat(ecc_errors).orR 95 io.error.bits.paddr := Cat(io.read.bits.idx, 0.U(pgUntagBits.W)) 148 io.errors(w) <> meta(w).io.error
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/XiangShan/src/main/scala/xiangshan/cache/ |
H A D | CacheInstruction.scala | 146 val error = Flipped(ValidIO(new L1CacheErrorInfo)) constant 275 val error = DelayNWithValid(io.error, 1) constant 276 when(error.bits.report_to_beu && error.valid) { 278 io.csr.update.w.bits.data := error.asUInt
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/XiangShan/src/main/scala/xiangshan/frontend/icache/ |
H A D | ICacheCtrlUnit.scala | 91 def error: UInt = 7.U(width.W) method 207 eccctrl.istatus := eccctrlInjStatus.error 253 when(x.istatus === eccctrlInjStatus.injected || x.istatus === eccctrlInjStatus.error) { 269 x.istatus := eccctrlInjStatus.error 273 x.istatus := eccctrlInjStatus.error
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H A D | ICache.scala | 558 val error: Valid[L1CacheErrorInfo] = ValidIO(new L1CacheErrorInfo) constant 740 io.error.bits <> RegEnable( 745 io.error.valid := RegNext(errors_valid, false.B)
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/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/ |
H A D | MainPipe.scala | 64 val error = Bool() constant 96 req.error := false.B 198 val error = Output(ValidIO(new L1CacheErrorInfo)) constant 340 …yMap((w: Int) => s1_meta_valids(w) && dcacheParameters.tagCode.decode(encTag_resp(w)).error).asUInt 354 … = ParallelMux(s1_tag_ecc_match_way.asBools, (0 until nWays).map(w => io.extra_meta_resp(w).error)) 420 val s2_l2_error = Mux(io.refill_info.valid, io.refill_info.bits.error, s2_req.error) 826 atomic_hit_resp.error := s3_error 835 atomic_replay_resp.error := false.B 995 io.error := 0.U.asTypeOf(ValidIO(new L1CacheErrorInfo)) 997 io.error.valid := s3_error && GatedValidRegNext(s2_fire && !s2_should_not_report_ecc_error) [all …]
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H A D | AtomicsReplayUnit.scala | 112 resp_error := io.pipe_resp.bits.error 124 io.lsu.resp.bits.error := resp_error
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H A D | MissQueue.scala | 101 val error = Bool() constant 455 val error = RegInit(false.B) constant 535 error := false.B 625 error := io.mem_grant.bits.denied || io.mem_grant.bits.corrupt || error 748 …io.refill_to_ldq.bits.error := RegEnable(io.mem_grant.bits.corrupt || io.mem_grant.bits.denied, re… 833 io.refill_info.bits.error := error 846 io.forwardInfo.corrupt := error
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H A D | Probe.scala | 106 pipe_req.error := false.B
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/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/ |
H A D | LoadPipe.scala | 81 val error = Output(ValidIO(new L1CacheErrorInfo)) constant 220 …) => meta_resp(w).coh.isValid() && dcacheParameters.tagCode.decode(s1_enctag_resp(w)).error).asUInt 280 …ParallelMux(s1_tag_match_way_dup_dc.asBools, (0 until nWays).map(w => io.extra_meta_resp(w).error)) 544 io.error := 0.U.asTypeOf(ValidIO(new L1CacheErrorInfo)) 545 io.error.bits.report_to_beu := (s3_tag_error || s3_data_error) && s3_valid 546 io.error.bits.paddr := s3_paddr 547 io.error.bits.source.tag := s3_tag_error 548 io.error.bits.source.data := s3_data_error 549 io.error.bits.source.l2 := s3_flag_error 550 io.error.bits.opType.load := true.B [all …]
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/XiangShan/src/test/scala/top/ |
H A D | SimMMIO.scala | 56 val error = LazyModule(new AXI4Error(illegalRange)) constant 65 error.node := axiBus
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/XiangShan/src/main/scala/xiangshan/cache/dcache/storepipe/ |
H A D | StorePipe.scala | 82 val error = Output(ValidIO(new L1CacheErrorInfo)) constant 86 io.error := 0.U.asTypeOf(ValidIO(new L1CacheErrorInfo))
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/XiangShan/src/main/scala/xiangshan/ |
H A D | XSCore.scala | 206 …memBlock.io.inner_beu_errors_icache <> frontend.io.error.bits.toL1BusErrorUnitInfo(frontend.io.err… 267 io.beu_errors.dcache <> memBlock.io.error.bits.toL1BusErrorUnitInfo(memBlock.io.error.valid)
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H A D | L2Top.scala | 337 beu.module.io.errors.l2.ecc_error.valid := l2.io.error.valid 338 beu.module.io.errors.l2.ecc_error.bits := l2.io.error.address
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/XiangShan/src/main/scala/xiangshan/cache/dcache/ |
H A D | DCacheWrapper.scala | 360 …val error = Bool() // cache line has been marked as corrupted by l2 / ecc error detected when store constant 475 val error = Bool() // all kinds of errors, include tag error constant 497 val error = Bool() // refilled data has been corrupted constant 561 val error = Bool() constant 569 data, id, miss, replay, tag_error, error) 587 val error = Bool() constant 812 val error = ValidIO(new L1CacheErrorInfo) constant 1065 val errors = ldu.map(_.io.error) ++ // load error 1066 Seq(mainPipe.io.error) // store / misc error 1068 io.error.bits <> RegEnable( [all …]
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H A D | Uncache.scala | 126 r.error := false.B
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/XiangShan/src/main/scala/xiangshan/frontend/ |
H A D | Frontend.scala | 87 val error = ValidIO(new L1CacheErrorInfo) constant 417 io.error <> RegNext(RegNext(icache.io.error))
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/XiangShan/src/main/scala/system/ |
H A D | SoC.scala | 393 val error = LazyModule(new TLError( constant 400 error.node := error_xbar.get
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/XiangShan/src/main/scala/xiangshan/cache/dcache/data/ |
H A D | DuplicatedDataArray.scala | 161 row_error(r)(k) := dcacheParameters.dataCode.decode(data).error && RegNext(rmask(r))
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H A D | BankedDataArray.scala | 541 …x)(bank_index)(way_index).error_delayed := dcacheParameters.dataCode.decode(ecc_data_delayed).error 860 …x)(bank_index)(way_index).error_delayed := dcacheParameters.dataCode.decode(ecc_data_delayed).error
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/XiangShan/src/main/scala/xiangshan/mem/ |
H A D | MemBlock.scala | 315 val error = ValidIO(new L1CacheErrorInfo) constant 401 io.error <> DelayNWithValid(dcache.io.error, 2) 403 io.error.bits.report_to_beu := false.B 404 io.error.valid := false.B
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/XiangShan/src/main/scala/xiangshan/mem/pipeline/ |
H A D | AtomicsUnit.scala | 365 dcache_resp_error := io.dcache.resp.bits.error
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/XiangShan/src/main/scala/xiangshan/cache/mmu/ |
H A D | MMUBundle.scala | 1054 …get((i+1)*ecc_info._2-1, i*ecc_info._2), data((i+1)*ecc_block-1, i*ecc_block))).error else false.B} 1058 …c.get(ecc_info._1-1, ecc_info._2*ecc_info._3), data(data.getWidth-1, ecc_info._3*ecc_block))).error
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/XiangShan/src/main/scala/xiangshan/backend/ |
H A D | Backend.scala | 946 for (((name, error), _) <- criticalErrors.zipWithIndex) { 947 XSError(error, s"critical error: $name \n")
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